Implementation of a Tensor Processing Unit for embedded systems and the IoT.
☆571Jan 5, 2019Updated 7 years ago
Alternatives and similar repositories for tinyTPU
Users that are interested in tinyTPU are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Small-scale Tensor Processing Unit built on an FPGA☆228Aug 4, 2019Updated 6 years ago
- IC implementation of TPU☆156Dec 18, 2019Updated 6 years ago
- Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…☆273May 6, 2023Updated 3 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆174Jul 25, 2019Updated 6 years ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆176Jun 9, 2023Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A open source reimplementation of Google's Tensor Processing Unit (TPU).☆775Dec 6, 2017Updated 8 years ago
- IC implementation of Systolic Array for TPU☆366Oct 21, 2024Updated last year
- ☆55Jan 14, 2021Updated 5 years ago
- AI Chip project☆34Jul 14, 2021Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆174May 10, 2025Updated last year
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆453Dec 2, 2019Updated 6 years ago
- A general framework for optimizing DNN dataflow on systolic array☆40Jan 2, 2021Updated 5 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Oct 7, 2020Updated 5 years ago
- An OpenCL-based FPGA Accelerator for Convolutional Neural Networks☆1,385Feb 14, 2022Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Deep Learning Accelerator (Convolution Neural Networks)☆200Dec 15, 2017Updated 8 years ago
- Berkeley's Spatial Array Generator☆1,405Jun 30, 2026Updated 3 weeks ago
- ☆261Apr 8, 2024Updated 2 years ago
- Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks☆626Jan 3, 2020Updated 6 years ago
- Hardware accelerator for convolutional neural networks☆76Aug 9, 2022Updated 3 years ago
- ☆73Dec 12, 2018Updated 7 years ago
- 在FPGA上面实现一个NPU计算单元。能够执行 矩阵运算(ADD/ADDi/ADDs/MULT/MULTi/DOT等)、图像处理运算(CONV/POOL等)、非线性映射(RELU/TANH/SIGM等)。☆321Aug 16, 2018Updated 7 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆257Apr 10, 2023Updated 3 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆179Mar 5, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆229Apr 22, 2019Updated 7 years ago
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 12 years ago
- ☆128Jul 22, 2020Updated 6 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆387Jan 20, 2025Updated last year
- Chisel implementation of Neural Processing Unit for System on the Chip☆34May 22, 2026Updated 2 months ago
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆390Dec 27, 2023Updated 2 years ago
- AIChip 2021 project, NCKU☆18May 6, 2021Updated 5 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆184Dec 14, 2019Updated 6 years ago
- Superscalar Out-of-Order NPU Design on FPGA☆15May 17, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Verilog implementation of Softmax function☆82Jul 27, 2022Updated 3 years ago
- An Eyeriss Chip (researched by MIT, a CNN accelerator) simulator and New DNN framework "Hive"☆227Dec 22, 2020Updated 5 years ago
- Open, Modular, Deep Learning Accelerator☆357Apr 10, 2024Updated 2 years ago
- RTL implementation of Flex-DPE.☆117Feb 22, 2020Updated 6 years ago
- Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"☆776May 26, 2017Updated 9 years ago
- Open-source of MSD framework☆16Sep 12, 2023Updated 2 years ago
- Tensor Processing Unit implementation in Verilog☆14Mar 18, 2025Updated last year