Alternatives and similar repositories for tinyTPU

Users that are interested in tinyTPU are comparing it to the libraries listed below

• cameronshinn / tiny-tpu
  Small-scale Tensor Processing Unit built on an FPGA
  ☆191Updated 5 years ago
• IBM / AccDNN
  A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
  ☆422Updated 5 years ago
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆376Updated 2 weeks ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆504Updated 4 months ago
• spcl / gemm_hls
  Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
  ☆347Updated 5 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆629Updated this week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆581Updated 2 weeks ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆426Updated last month
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆435Updated this week
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆251Updated 8 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆568Updated 2 months ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆810Updated 3 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,308Updated this week
• embedeep / Free-TPU
  Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…
  ☆259Updated 2 years ago
• definelicht / hlslib
  A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
  ☆319Updated 5 months ago
• LeiWang1999 / ZYNQ-NVDLA
  NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.
  ☆338Updated last year
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆645Updated 2 years ago
• cea-wind / SimpleTPU
  A FPGA Based CNN accelerator, following Google's TPU V1.
  ☆155Updated 5 years ago
• embedeep / FREE-TPU-V3plus-for-FPGA
  FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
  ☆151Updated 2 years ago
• Xilinx / XilinxBoardStore
  ☆288Updated 3 weeks ago
• hsharma35 / dnnweaver2
  Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.
  ☆215Updated 6 years ago
• ucb-bar / berkeley-hardfloat
  ☆331Updated 9 months ago
• fpgasystems / spooNN
  FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)
  ☆273Updated 5 years ago
• aliemo / transfomers-silicon-research
  Research and Materials on Hardware implementation of Transformer Model
  ☆265Updated 3 months ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆497Updated 7 months ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆353Updated last year
• pyuvm / pyuvm
  The UVM written in Python
  ☆434Updated this week
• Xilinx / Vitis_Accel_Examples
  Vitis_Accel_Examples
  ☆546Updated last week
• Xilinx / Vitis-HLS-Introductory-Examples
  ☆687Updated 3 weeks ago
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆222Updated last year