jofrfu / tinyTPULinks
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
☆466Updated 6 years ago
Alternatives and similar repositories for tinyTPU
Users that are interested in tinyTPU are comparing it to the libraries listed below
Sorting:
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆421Updated 5 years ago
- Small-scale Tensor Processing Unit built on an FPGA☆188Updated 5 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆345Updated 4 months ago
- Bus bridges and other odds and ends☆563Updated last month
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆272Updated 5 years ago
- synthesiseable ieee 754 floating point library in verilog☆638Updated 2 years ago
- IC implementation of Systolic Array for TPU☆246Updated 7 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆500Updated 3 months ago
- Common SystemVerilog components☆623Updated this week
- Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…☆258Updated 2 years ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆373Updated 3 weeks ago
- Verilog AXI stream components for FPGA implementation☆808Updated 3 months ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆319Updated 4 months ago
- Implementation of CNN using Verilog☆217Updated 7 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆467Updated 3 years ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆429Updated 2 weeks ago
- ☆288Updated this week
- A FPGA Based CNN accelerator, following Google's TPU V1.☆153Updated 5 years ago
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆336Updated last year
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆426Updated 3 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,287Updated last week
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆349Updated last year
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆146Updated last year
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆269Updated last month
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆152Updated 11 months ago
- The OpenPiton Platform☆707Updated 2 weeks ago
- A convolutional neural network implemented in hardware (verilog)☆157Updated 7 years ago
- Berkeley's Spatial Array Generator☆957Updated last month
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆494Updated 6 months ago
- Convolutional accelerator kernel, target ASIC & FPGA☆205Updated 2 years ago