Alternatives and similar repositories for tinyTPU:

Users that are interested in tinyTPU are comparing it to the libraries listed below

• IBM / AccDNN
  A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
  ☆405Updated 5 years ago
• cameronshinn / tiny-tpu
  Small-scale Tensor Processing Unit built on an FPGA
  ☆141Updated 5 years ago
• spcl / gemm_hls
  Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
  ☆320Updated last week
• embedeep / Free-TPU
  Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…
  ☆243Updated last year
• definelicht / hlslib
  A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
  ☆311Updated last week
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆178Updated 3 months ago
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆351Updated 2 weeks ago
• drichmond / RISC-V-On-PYNQ
  RISC-V Integration for PYNQ
  ☆167Updated 5 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆560Updated 2 weeks ago
• fpgasystems / spooNN
  FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)
  ☆263Updated 5 years ago
• Xilinx / XilinxBoardStore
  ☆272Updated last week
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆208Updated last year
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆511Updated last week
• alan4186 / Hardware-CNN
  A convolutional neural network implemented in hardware (verilog)
  ☆155Updated 7 years ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆301Updated 2 weeks ago
• soDLA-publishment / soDLA
  Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated
  ☆226Updated this week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆451Updated 3 months ago
• cea-wind / SimpleTPU
  A FPGA Based CNN accelerator, following Google's TPU V1.
  ☆130Updated 5 years ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆542Updated this week
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆394Updated this week
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆189Updated last month
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆178Updated 4 years ago
• AniketBadhan / Convolutional-Neural-Network
  Implementation of CNN using Verilog
  ☆200Updated 7 years ago
• bu-icsg / dana
  Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  ☆209Updated 5 years ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆550Updated last year
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆399Updated last week
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆266Updated 2 months ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆769Updated 5 months ago
• lastweek / fpga_readings
  Recipe for FPGA cooking
  ☆288Updated 4 months ago
• changwoolee / lenet5_hls
  FPGA Accelerator for CNN using Vivado HLS
  ☆308Updated 3 years ago