Implementation of a Tensor Processing Unit for embedded systems and the IoT.
☆551Jan 5, 2019Updated 7 years ago
Alternatives and similar repositories for tinyTPU
Users that are interested in tinyTPU are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Small-scale Tensor Processing Unit built on an FPGA☆221Aug 4, 2019Updated 6 years ago
- IC implementation of TPU☆149Dec 18, 2019Updated 6 years ago
- Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…☆273May 6, 2023Updated 2 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆173Jul 25, 2019Updated 6 years ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆171Jun 9, 2023Updated 2 years ago
- A open source reimplementation of Google's Tensor Processing Unit (TPU).☆741Dec 6, 2017Updated 8 years ago
- IC implementation of Systolic Array for TPU☆343Oct 21, 2024Updated last year
- ☆52Jan 14, 2021Updated 5 years ago
- AI Chip project☆34Jul 14, 2021Updated 4 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Oct 7, 2020Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆164May 10, 2025Updated 10 months ago
- Hardware accelerator for convolutional neural networks☆67Aug 9, 2022Updated 3 years ago
- A general framework for optimizing DNN dataflow on systolic array☆39Jan 2, 2021Updated 5 years ago
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆447Dec 2, 2019Updated 6 years ago
- An OpenCL-based FPGA Accelerator for Convolutional Neural Networks☆1,370Feb 14, 2022Updated 4 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆199Dec 15, 2017Updated 8 years ago
- Berkeley's Spatial Array Generator☆1,251Updated this week
- ☆243Apr 8, 2024Updated last year
- Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks☆622Jan 3, 2020Updated 6 years ago
- ☆73Dec 12, 2018Updated 7 years ago
- 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。☆299Aug 16, 2018Updated 7 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆248Apr 10, 2023Updated 2 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆170Mar 5, 2025Updated last year
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆227Apr 22, 2019Updated 6 years ago
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 11 years ago
- ☆125Jul 22, 2020Updated 5 years ago
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆386Dec 27, 2023Updated 2 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆376Jan 20, 2025Updated last year
- AIChip 2021 project, NCKU☆17May 6, 2021Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆182Dec 14, 2019Updated 6 years ago
- Verilog implementation of Softmax function☆80Jul 27, 2022Updated 3 years ago
- Superscalar Out-of-Order NPU Design on FPGA☆12May 17, 2024Updated last year
- An Eyeriss Chip (researched by MIT, a CNN accelerator) simulator and New DNN framework "Hive"☆221Dec 22, 2020Updated 5 years ago
- RTL implementation of Flex-DPE.☆116Feb 22, 2020Updated 6 years ago
- Open-source of MSD framework☆16Sep 12, 2023Updated 2 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆26Jan 19, 2026Updated 2 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Dec 19, 2021Updated 4 years ago
- Open, Modular, Deep Learning Accelerator☆334Apr 10, 2024Updated last year
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated last year