jofrfu / tinyTPU
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
☆402Updated 5 years ago
Related projects ⓘ
Alternatives and complementary repositories for tinyTPU
- Small-scale Tensor Processing Unit built on an FPGA☆121Updated 5 years ago
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆398Updated 4 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆307Updated 2 years ago
- DPU on PYNQ☆202Updated 9 months ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆343Updated last week
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆261Updated 4 years ago
- RISC-V Integration for PYNQ☆165Updated 5 years ago
- Vitis HLS Library for FINN☆181Updated last week
- A open source reimplementation of Google's Tensor Processing Unit (TPU).☆364Updated 6 years ago
- Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…☆240Updated last year
- A convolutional neural network implemented in hardware (verilog)☆151Updated 7 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆303Updated 6 months ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆175Updated 4 years ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆260Updated 2 weeks ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆452Updated 7 months ago
- ☆256Updated this week
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆206Updated 5 years ago
- Dataflow QNN inference accelerator examples on FPGAs☆185Updated 2 weeks ago
- Implementation of CNN using Verilog☆187Updated 7 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆438Updated 3 weeks ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆379Updated this week
- A FPGA Based CNN accelerator, following Google's TPU V1.☆120Updated 5 years ago
- Binarized Convolutional Neural Networks on Software-Programmable FPGAs☆302Updated 4 years ago
- IC implementation of Systolic Array for TPU☆152Updated last month
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆389Updated 3 weeks ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆200Updated last year
- BaseJump STL: A Standard Template Library for SystemVerilog☆526Updated this week
- Vitis_Accel_Examples☆506Updated this week
- ☆242Updated 4 years ago
- Build Customized FPGA Implementations for Vivado☆294Updated this week