A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
☆105Dec 14, 2023Updated 2 years ago
Alternatives and similar repositories for CNN_for_SLR
Users that are interested in CNN_for_SLR are comparing it to the libraries listed below
Sorting:
- FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.☆186Jan 28, 2017Updated 9 years ago
- This project implemented an unoptimized simple convolutional neural network in ZYNQ's PL and realized data transmission through axidma dr…☆12Aug 5, 2018Updated 7 years ago
- Simulating implement of LeNet network on Zynq-7020 FPGA☆30Mar 11, 2019Updated 6 years ago
- hls code zynq 7020 pynq z2 CNN☆89Mar 15, 2019Updated 6 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆195Mar 20, 2024Updated last year
- CNN acceleration on virtex-7 FPGA with verilog HDL☆475Feb 27, 2018Updated 8 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆116Jun 24, 2017Updated 8 years ago
- Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"☆768May 26, 2017Updated 8 years ago
- This is an open CNN accelerator for everyone to use☆14Jul 15, 2019Updated 6 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Jun 3, 2019Updated 6 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆111Apr 3, 2020Updated 5 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆182Jun 20, 2024Updated last year
- 中文：☆108Nov 29, 2019Updated 6 years ago
- Convolutional Neural Net written for implementation on an FPGA☆21Jun 26, 2017Updated 8 years ago
- A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard☆896Jul 29, 2024Updated last year
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆252Dec 29, 2018Updated 7 years ago
- This repository contains a SDSoC Project which includes an implementation of a 3-layered artificial neural network (testphase only). It c…☆12Oct 7, 2016Updated 9 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Jan 4, 2018Updated 8 years ago
- verilog CNN generator for FPGA☆34Jan 4, 2021Updated 5 years ago
- Verilog Convolutional Neural Network on PYNQ☆28Apr 2, 2018Updated 7 years ago
- 使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用☆582Jun 18, 2018Updated 7 years ago
- Implementation of YOLOv3-tiny + Depthwise Separable Convolution on FPGA☆33Mar 2, 2022Updated 4 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆164Dec 13, 2020Updated 5 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆28Nov 5, 2021Updated 4 years ago
- Digital Design Lab Spring 2019 Final Project☆13Jun 17, 2019Updated 6 years ago
- CNN Accelerator in Frequency Domain☆12Feb 22, 2020Updated 6 years ago
- ☆14Mar 13, 2023Updated 2 years ago
- a Real-time image recognition project with RTL accelerator and ZYNQ Architecture☆66Apr 8, 2024Updated last year
- Light-weighted neural network inference for object detection on small-scale FPGA board☆92May 25, 2019Updated 6 years ago
- Systolic-array based Deep Learning Accelerator generator☆28Dec 11, 2020Updated 5 years ago
- Simulating implement of vgg16 network on Zynq-7020 FPGA☆43Mar 11, 2019Updated 6 years ago
- A real time Histogram of Oriented Gradients Implementation on FPGA☆32Jul 21, 2018Updated 7 years ago
- ☆73Dec 12, 2018Updated 7 years ago
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆283Dec 5, 2019Updated 6 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆198Dec 15, 2017Updated 8 years ago
- HDL implementation of a pipelined multilayer perceptron (neural network)☆17Sep 14, 2015Updated 10 years ago
- The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track☆91Nov 25, 2018Updated 7 years ago
- Implement Tiny YOLO v3 on ZYNQ☆312Apr 14, 2025Updated 10 months ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆23May 20, 2019Updated 6 years ago