evan199893 / TPU_systolic_array_HW_acceleratorLinks
Tensor Processing Unit implementation in Verilog
☆8Updated 4 months ago
Alternatives and similar repositories for TPU_systolic_array_HW_accelerator
Users that are interested in TPU_systolic_array_HW_accelerator are comparing it to the libraries listed below
Sorting:
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆13Updated 2 years ago
- This project is to design yolo AI accelerator in verilog HDL.☆20Updated 10 months ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- Router 1 x 3 verilog implementation☆13Updated 3 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆25Updated 2 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆10Updated last year
- DMA controller for CNN accelerator☆13Updated 8 years ago
- ☆10Updated 5 years ago
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆14Updated 4 months ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆10Updated 6 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- ☆34Updated 6 years ago
- ☆14Updated 2 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆34Updated 3 years ago
- UVM Testbench for synchronus fifo☆17Updated 4 years ago
- 包 括同步FIFO(输入输出位宽相同),异步FIFO(输入输出位宽相同),异步FIFO(能实现输出数据位宽是输入数据位宽的1/2或2倍)☆20Updated 2 years ago
- This repository contains full code of Softmax Layer in Verilog☆18Updated 5 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆21Updated 11 months ago
- A systolic array matrix multiplier☆24Updated 5 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆13Updated 6 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆23Updated 5 years ago
- EE577b-Course-Project☆17Updated 5 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆12Updated 5 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆19Updated 7 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆22Updated 6 months ago