Tensor Processing Unit implementation in Verilog
☆16Aug 12, 2026Updated this week
Alternatives and similar repositories for TPU_systolic_array_HW_accelerator
Users that are interested in TPU_systolic_array_HW_accelerator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 5 years ago
- Systolic Array implementation for ASIC Course☆15Nov 26, 2023Updated 2 years ago
- Energy-Efficient Inference Accelerator for Memory-Augmented Neural Networks on an FPGA (DATE-19)☆15Jan 29, 2021Updated 5 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆51Jun 24, 2022Updated 4 years ago
- AI Chip project☆34Jul 14, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Superscalar Out-of-Order NPU Design on FPGA☆16May 17, 2024Updated 2 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆18Feb 27, 2021Updated 5 years ago
- ☆11Jun 28, 2020Updated 6 years ago
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- Eyeriss Hardware Accelerator for Machine Learning☆13May 29, 2022Updated 4 years ago
- 基于FP16的二维脉动阵列电路设计☆13Feb 23, 2023Updated 3 years ago
- MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement☆16Nov 4, 2022Updated 3 years ago
- Template for project1 TPU☆23May 1, 2021Updated 5 years ago
- a student trainning project for HLS and transformer☆11Oct 19, 2022Updated 3 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆47Sep 26, 2023Updated 2 years ago
- Implementation for paper "BATMANN: A Binarized-All-Through Memory-Augmented Neural Network for Efficient In-Memory Computing"☆12Jan 12, 2022Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆175May 10, 2025Updated last year
- verilog/FPGA hardware description for very simple GPU☆17Apr 9, 2019Updated 7 years ago
- SystemVerilog Implementations of CUDA/TensorCore/TPU GEMM Operations☆21Apr 12, 2026Updated 4 months ago
- Simple test of ARM NEON code. Performs a blit to the framebuffer.☆15Jul 23, 2013Updated 13 years ago
- Router 1 x 3 verilog implementation☆15Sep 5, 2021Updated 4 years ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 5 years ago
- IC implementation of Systolic Array for TPU☆369Oct 21, 2024Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- A convolution based 3x3 GaussianBlur implementation using ARM NEON assembly engine☆10Jan 20, 2019Updated 7 years ago
- An automated HDC platform☆11Mar 16, 2026Updated 5 months ago
- AXI-4 RAM Tester Component☆21Aug 5, 2020Updated 6 years ago
- ai_accelerator_basic_for_student (no solve)☆18Mar 27, 2020Updated 6 years ago
- ☆31Aug 8, 2020Updated 6 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals,this SoC run a CNN. The…☆14Mar 30, 2023Updated 3 years ago
- Verilog CAN controller that is compatible to the SJA 1000.☆19Apr 17, 2021Updated 5 years ago
- USB2.0 Device Controller IP Core☆18Aug 18, 2023Updated 3 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆15Jul 28, 2021Updated 5 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Implementation of Sobel Filter in Verilog☆29Mar 10, 2017Updated 9 years ago
- 简单易用的微信小程序倒计时库☆15May 15, 2018Updated 8 years ago
- An 8 input interrupt controller written in Verilog.☆30Mar 22, 2012Updated 14 years ago
- Floating-point matrix multiplication implementation (arbitrary precision)☆18Aug 3, 2021Updated 5 years ago
- ☆55Jan 14, 2021Updated 5 years ago
- Hardware accelerator for convolutional neural networks☆76Aug 9, 2022Updated 4 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Oct 7, 2020Updated 5 years ago