zhangzek / 3x3_matrix_Systolic_Array_multiplierLinks
3×3脉动阵列乘法器
☆45Updated 5 years ago
Alternatives and similar repositories for 3x3_matrix_Systolic_Array_multiplier
Users that are interested in 3x3_matrix_Systolic_Array_multiplier are comparing it to the libraries listed below
Sorting:
- verilog实现TPU中的脉动阵列计算卷积的module☆121Updated 2 months ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆163Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆216Updated 2 years ago
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- AXI总线连接器☆100Updated 5 years ago
- IC Verification & SV Demo☆54Updated 3 years ago
- A verilog implementation for Network-on-Chip☆74Updated 7 years ago
- ☆34Updated 6 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆34Updated 5 years ago
- ☆41Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆83Updated 4 months ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆65Updated 10 months ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- AXI DMA 32 / 64 bits☆115Updated 10 years ago
- ☆113Updated 4 years ago
- CNN accelerator implemented with Spinal HDL☆150Updated last year
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆155Updated last year
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆76Updated last year
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆50Updated 11 months ago
- FFT generator using Chisel☆61Updated 3 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- Convolutional Neural Network Using High Level Synthesis☆86Updated 4 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆64Updated 6 years ago
- ☆17Updated last year
- Convolutional Neural Network RTL-level Design☆59Updated 3 years ago
- IC implementation of Systolic Array for TPU☆257Updated 8 months ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆41Updated 2 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆24Updated 2 years ago