zhangzek / 3x3_matrix_Systolic_Array_multiplierLinks
3×3脉动阵列乘法器
☆49Updated 6 years ago
Alternatives and similar repositories for 3x3_matrix_Systolic_Array_multiplier
Users that are interested in 3x3_matrix_Systolic_Array_multiplier are comparing it to the libraries listed below
Sorting:
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆177Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆143Updated 7 months ago
- AXI总线连接器☆105Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆109Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆235Updated 2 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆39Updated 3 years ago
- upgrade to e203 (a risc-v core)☆45Updated 5 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆34Updated 5 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Updated 4 years ago
- ☆44Updated 4 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- AXI DMA 32 / 64 bits☆122Updated 11 years ago
- IC Verification & SV Demo☆54Updated 4 years ago
- ☆38Updated 6 years ago
- IC implementation of TPU☆140Updated 5 years ago
- ☆123Updated 5 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆120Updated 4 months ago
- achieve softmax in PYNQ with heterogeneous computing.☆67Updated 7 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆82Updated 2 years ago
- ☆71Updated 6 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆69Updated last year
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆62Updated last year
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆28Updated 3 years ago
- ☆72Updated 9 years ago
- IC implementation of Systolic Array for TPU☆311Updated last year
- FPGA/AES/LeNet/VGG16☆109Updated 7 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆33Updated 4 years ago
- 支持AXI总线协议的8k×8 SP SRAM☆26Updated 5 years ago