zhangzek / 3x3_matrix_Systolic_Array_multiplier
3×3脉动阵列乘法器
☆44Updated 5 years ago
Alternatives and similar repositories for 3x3_matrix_Systolic_Array_multiplier:
Users that are interested in 3x3_matrix_Systolic_Array_multiplier are comparing it to the libraries listed below
- verilog实现TPU中的脉动阵列计算卷积的module☆92Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆147Updated 5 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆70Updated last year
- ☆104Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆97Updated 4 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆34Updated 2 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆56Updated last month
- AXI总线连接器☆97Updated 5 years ago
- upgrade to e203 (a risc-v core)☆41Updated 4 years ago
- IC Verification & SV Demo☆52Updated 3 years ago
- AXI DMA 32 / 64 bits☆111Updated 10 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆60Updated 7 months ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆83Updated 5 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆41Updated 7 months ago
- tpu-systolic-array-weight-stationary☆23Updated 3 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆186Updated last year
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 5 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆179Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 4 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- An AXI4 crossbar implementation in SystemVerilog☆140Updated last month
- 数字IC秋招项目、手撕代码☆34Updated 11 months ago
- A verilog implementation for Network-on-Chip☆72Updated 7 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- FPGA/AES/LeNet/VGG16☆99Updated 6 years ago
- ☆31Updated 5 years ago
- ☆63Updated 6 years ago
- ☆33Updated 4 years ago