3×3脉动阵列乘法器
☆50Sep 18, 2019Updated 7 years ago
Alternatives and similar repositories for 3x3_matrix_Systolic_Array_multiplier
Users that are interested in 3x3_matrix_Systolic_Array_multiplier are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- verilog实现TPU中的脉动阵列计算卷积的module☆181May 10, 2025Updated last year
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 7 years ago
- (Verilog) A simple convolution layer implementation with systolic array structure☆14May 9, 2022Updated 4 years ago
- ☆73Dec 12, 2018Updated 7 years ago
- IC implementation of Systolic Array for TPU☆382Oct 21, 2024Updated 2 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆28Jul 4, 2019Updated 7 years ago
- Config files for my GitHub profile.☆14Apr 21, 2025Updated last year
- Tensor Processing Unit implementation in Verilog☆16Aug 12, 2026Updated 2 months ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆19Feb 27, 2021Updated 5 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 10 years ago
- eyeriss-chisel3☆41May 2, 2022Updated 4 years ago
- Clock Domain Crossing Design(use MCP formulation without feedback)基于MCP不带反馈的跨时钟域设计☆13Jan 3, 2020Updated 6 years ago
- 基于FP16的二维脉动阵列电路设计☆13Feb 23, 2023Updated 3 years ago
- SystemVerilog code for image processing tasks like demosaicing☆11Jun 28, 2020Updated 6 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- NoC based MPSoC☆11Jul 17, 2014Updated 12 years ago
- ☆58Jan 14, 2021Updated 5 years ago
- My MSc Thesis: Low Latency Router Microarchitecture for Network-on-Chip Implemented on an FPGA☆13Jun 26, 2018Updated 8 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆249Oct 16, 2025Updated last year
- ☆24May 18, 2022Updated 4 years ago
- This repo contains a parameterizable TPU-like design (in Verilog) that will be overlayed onto an FPGA (probably PYNQ). We plan to add thi…☆15Jul 17, 2022Updated 4 years ago
- Python code to show how a systolic array works. Written for https://medium.com/@antonpaquin/whats-inside-a-tpu-c013eb51973e☆29Jun 8, 2018Updated 8 years ago
- Energy-Efficient Inference Accelerator for Memory-Augmented Neural Networks on an FPGA (DATE-19)☆15Jan 29, 2021Updated 5 years ago
- 🎞️ NoC router in Verilog with FIFO☆15Sep 1, 2022Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- soc integration script and integration smoke script☆24Sep 12, 2022Updated 4 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 12 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆37Jan 12, 2021Updated 5 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆21Jul 9, 2024Updated 2 years ago
- ☆10May 26, 2023Updated 3 years ago
- ☆14Jun 30, 2019Updated 7 years ago
- Collection of different communication methods for chip mulitprocessors☆13Jul 20, 2026Updated 3 months ago
- Systolic-array based Deep Learning Accelerator generator☆29Dec 11, 2020Updated 5 years ago
- Design for 4 x 4 Matrix Multiplication using Verilog☆33Jun 9, 2015Updated 11 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Verilog Sigmoid and Tanh functions which can be configured and added to your neural network project☆16Mar 9, 2020Updated 6 years ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 7 years ago
- Main repo of the OOP class☆11Oct 16, 2017Updated 9 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆179Jul 25, 2019Updated 7 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆53Jun 24, 2022Updated 4 years ago
- 5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany☆16Dec 4, 2025Updated 10 months ago
- ☆16Dec 4, 2021Updated 4 years ago