Alternatives and similar repositories for Systolic-Array

Users that are interested in Systolic-Array are comparing it to the libraries listed below

• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆51Updated 9 months ago
• hyoukjun / microswitch-noc
  ☆27Updated 5 years ago
• AIC2021 / AIC2021_TPU_Template
  Template for project1 TPU
  ☆19Updated 4 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆65Updated 6 years ago
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆28Updated 4 years ago
• ljgibbslf / basic_cache_core
  ☆29Updated 4 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆79Updated 3 years ago
• VeriGOOD-ML / public
  ☆60Updated 2 months ago
• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆22Updated 3 years ago
• kuladeepsaireddy / OpenNoc
  ☆34Updated 6 years ago
• hlslibs / hls_tutorials
  Tutorials on HLS Design
  ☆52Updated 5 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆41Updated 3 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆24Updated 4 years ago
• meton-robean / Vector_MulAdd_Accelerator
  vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
  ☆53Updated 5 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆57Updated 3 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆65Updated 5 years ago
• pulp-platform / fpu
  ☆51Updated 6 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆58Updated this week
• KyleParkJong / Network-on-Chip-Simulator
  Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
  ☆29Updated last year
• kkiningh / cs231n-project
  CNN accelerator
  ☆27Updated 8 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆74Updated 7 years ago
• spcl / rapidchiplet
  A toolchain for rapid design space exploration of chiplet architectures
  ☆53Updated 2 months ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆35Updated 4 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆46Updated 4 months ago
• pulp-platform / ITA
  ☆47Updated 2 months ago
• tharunchitipolu / Dadda-Multiplier-using-CSA
  Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
  ☆34Updated last year
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆40Updated 2 years ago
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• sharc-lab / FPGA_ECE8893
  ☆35Updated 3 months ago
• sfu-arch / SpGEMM
  ☆36Updated 4 years ago