course design
☆23Feb 28, 2018Updated 8 years ago
Alternatives and similar repositories for Systolic-Array
Users that are interested in Systolic-Array are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 10 years ago
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 7 years ago
- ☆15Mar 24, 2023Updated 3 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆28Jul 4, 2019Updated 7 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆20Feb 27, 2025Updated last year
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- openai-gym style RL benchmark for interconnection network congestion control study☆17May 12, 2022Updated 4 years ago
- ☆73Dec 12, 2018Updated 7 years ago
- Netrace: a network packet trace reader☆16Jun 16, 2014Updated 12 years ago
- MLFlow End to End Workshop at Chandigarh University☆11Feb 3, 2023Updated 3 years ago
- [WIP] ConfigX - Settings Management☆13Mar 6, 2024Updated 2 years ago
- NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators☆23Mar 20, 2025Updated last year
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆71Oct 14, 2025Updated 11 months ago
- ☆32Aug 21, 2021Updated 5 years ago
- IC implementation of TPU☆160Dec 18, 2019Updated 6 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆42Sep 21, 2021Updated 4 years ago
- ☆18Feb 13, 2021Updated 5 years ago
- RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor☆21Updated this week
- EBAZ4205 is Xilinx Zynq based mining board used in Ebang Ebit E9+ bitcoin miner machine.☆10Jan 18, 2022Updated 4 years ago
- Tiny MATLAB-to-C converter (TMC Compiler)☆13Oct 26, 2020Updated 5 years ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 3 years ago
- Template for project1 TPU☆23May 1, 2021Updated 5 years ago
- ☆12Mar 3, 2025Updated last year
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆30Oct 3, 2023Updated 2 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- WM8731 Audio CODEC using Verilog (DE2-115)☆11Jul 28, 2019Updated 7 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Jul 17, 2023Updated 3 years ago
- ACM TODAES Best Paper Award, 2022☆35Oct 24, 2023Updated 2 years ago
- SystemVerilog code for image processing tasks like demosaicing☆11Jun 28, 2020Updated 6 years ago
- ☆15May 24, 2025Updated last year
- ☆11Sep 7, 2023Updated 3 years ago
- WISHBONE Interconnect☆11Oct 1, 2017Updated 8 years ago
- ☆13May 28, 2021Updated 5 years ago
- YoloV6 for a bare Raspberry Pi using ncnn.☆10Jun 12, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆67Aug 28, 2026Updated 3 weeks ago
- ☆17Oct 15, 2023Updated 2 years ago
- Fork of Verilator with prebuilt Ubuntu binaries (https://www.veripool.org/wiki/verilator)☆24Jun 28, 2022Updated 4 years ago
- ☆13Jul 5, 2026Updated 2 months ago
- verilog实现TPU中的脉动阵列计算卷积的module☆175May 10, 2025Updated last year
- PCB design with the new MLX75027 VGA time of flight sensor☆13Dec 8, 2021Updated 4 years ago
- Code and models of the paper "FPGA accelerator for Gradient Boosting Decision Trees".☆15Mar 24, 2026Updated 5 months ago