nqHITSZ / Systolic-ArrayLinks
course design
☆23Updated 7 years ago
Alternatives and similar repositories for Systolic-Array
Users that are interested in Systolic-Array are comparing it to the libraries listed below
Sorting:
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆76Updated last month
- Template for project1 TPU☆21Updated 4 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆24Updated 4 years ago
- ☆71Updated 7 years ago
- HLS for Networks-on-Chip☆39Updated 4 years ago
- ☆57Updated 6 years ago
- ☆28Updated 6 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated 3 weeks ago
- eyeriss-chisel3☆40Updated 3 years ago
- Tutorials on HLS Design☆52Updated 5 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- ☆40Updated 6 years ago
- ☆31Updated 5 years ago
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆39Updated last year
- Public release☆58Updated 6 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 10 months ago
- A floating-point matrix multiplication implemented in hardware☆32Updated 5 years ago
- ☆41Updated 9 months ago
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Updated 4 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- ☆65Updated 8 months ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆36Updated 2 years ago
- ☆39Updated 2 weeks ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 3 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- The official NaplesPU hardware code repository☆21Updated 6 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆71Updated 5 months ago
- ☆37Updated 2 months ago
- CNN accelerator☆28Updated 8 years ago