nqHITSZ / Systolic-ArrayLinks
course design
☆22Updated 7 years ago
Alternatives and similar repositories for Systolic-Array
Users that are interested in Systolic-Array are comparing it to the libraries listed below
Sorting:
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆59Updated last year
- Template for project1 TPU☆19Updated 4 years ago
- ☆27Updated 5 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆54Updated 5 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 4 years ago
- ☆37Updated 6 months ago
- Tutorials on HLS Design☆52Updated 5 years ago
- HLS for Networks-on-Chip☆36Updated 4 years ago
- ☆68Updated 6 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆31Updated last year
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- The official NaplesPU hardware code repository☆19Updated 6 years ago
- Systolic array implementations for Cholesky, LU, and QR decomposition☆46Updated 10 months ago
- ☆54Updated 6 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- cycle accurate Network-on-Chip Simulator☆30Updated 2 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- ☆34Updated 4 months ago
- Public release☆56Updated 6 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆17Updated 4 years ago
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆35Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- eyeriss-chisel3☆41Updated 3 years ago
- ☆36Updated 4 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆43Updated 9 months ago
- A toolchain for rapid design space exploration of chiplet architectures☆61Updated 2 months ago
- ☆67Updated 4 years ago