aravinds92 / Systolic-Array
Systolic array based hardware for Image processing on the SPARTAN-6 FPGA
☆12Updated 8 years ago
Related projects ⓘ
Alternatives and complementary repositories for Systolic-Array
- CNN accelerator☆26Updated 7 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆21Updated 5 years ago
- ☆22Updated 5 years ago
- A systolic array matrix multiplier☆23Updated 5 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆17Updated 11 years ago
- MAESTRO binary release☆22Updated 5 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- MAERI public release☆31Updated 3 years ago
- ☆10Updated 5 months ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 4 years ago
- ☆32Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆23Updated last month
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆44Updated 2 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Systolic-array based Deep Learning Accelerator generator☆24Updated 3 years ago
- The Verilog source code for DRUM approximate multiplier.☆28Updated last year
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆9Updated 4 years ago
- CNN Accelerator in Frequency Domain☆10Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆24Updated 4 years ago
- ☆17Updated 6 years ago
- eyeriss-chisel3☆39Updated 2 years ago
- ☆13Updated 4 years ago
- CNN accelerator using NoC architecture☆15Updated 5 years ago
- ☆20Updated 2 years ago
- A general framework for optimizing DNN dataflow on systolic array☆33Updated 3 years ago
- first-order deep learning accelerator model☆18Updated 6 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- HLS for Networks-on-Chip☆31Updated 3 years ago