aravinds92 / Systolic-ArrayLinks
Systolic array based hardware for Image processing on the SPARTAN-6 FPGA
☆12Updated 9 years ago
Alternatives and similar repositories for Systolic-Array
Users that are interested in Systolic-Array are comparing it to the libraries listed below
Sorting:
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆26Updated 6 years ago
- ☆72Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- CNN accelerator☆27Updated 8 years ago
- A general framework for optimizing DNN dataflow on systolic array☆39Updated 4 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- MAESTRO binary release☆22Updated 5 years ago
- ☆16Updated 2 years ago
- MAERI public release☆31Updated 3 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 6 months ago
- ☆34Updated 6 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- ☆58Updated 5 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆29Updated 2 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores☆12Updated 3 years ago
- ☆27Updated 5 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆31Updated 6 years ago
- Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …☆11Updated 2 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- ☆16Updated 4 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆21Updated 12 years ago
- ☆25Updated 2 years ago
- first-order deep learning accelerator model☆19Updated 7 years ago
- Template for project1 TPU☆19Updated 4 years ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆34Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- ☆17Updated 3 months ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 5 years ago
- An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool☆15Updated 8 years ago