aravinds92 / Systolic-Array
Systolic array based hardware for Image processing on the SPARTAN-6 FPGA
☆12Updated 8 years ago
Alternatives and similar repositories for Systolic-Array:
Users that are interested in Systolic-Array are comparing it to the libraries listed below
- CNN accelerator☆27Updated 7 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆22Updated 5 years ago
- MAESTRO binary release☆22Updated 5 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- ☆33Updated 5 years ago
- MAERI public release☆31Updated 3 years ago
- ☆24Updated 5 years ago
- A systolic array matrix multiplier☆24Updated 5 years ago
- ☆71Updated last year
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- Systolic-array based Deep Learning Accelerator generator☆25Updated 4 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- CNN Accelerator in Frequency Domain☆12Updated 4 years ago
- ☆13Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆17Updated 11 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 4 years ago
- ☆25Updated 9 months ago
- ☆3Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆67Updated 3 years ago
- ☆33Updated 3 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- NeuraChip Accelerator Simulator☆11Updated 9 months ago
- ☆16Updated last year
- Documentation for the entire CGRAFlow☆19Updated 3 years ago
- Designs for finalist teams of the DAC System Design Contest☆36Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆27Updated 3 months ago
- eyeriss-chisel3☆40Updated 2 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆11Updated 4 years ago