horizon-research / systolic-array-dataflow-optimizer

Related projects ⓘ

Alternatives and complementary repositories for systolic-array-dataflow-optimizer

• UCLA-VAST / FlexCNN
  ☆70Updated last year
• Accelergy-Project / processing-in-memory-design
  ☆24Updated 7 months ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆35Updated 4 years ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆30Updated last month
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆44Updated 2 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆59Updated 3 years ago
• GATECH-EIC / AutoDNNchip
  ☆69Updated 4 years ago
• CASR-HKU / AGNA-FCCM2023
  ☆12Updated 11 months ago
• dimdano / adapt
  Fast Emulation of Approximate DNN Accelerators in PyTorch
  ☆17Updated 8 months ago
• DNN-Accelerators / Open-Source-IPs
  ☆32Updated 5 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆42Updated 2 years ago
• CRAFT-THU / XB-Sim
  A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration
  ☆31Updated 2 years ago
• fffasttime / AnyPackingNet
  ☆24Updated 8 months ago
• CASR-HKU / DPACS
  ☆18Updated last year
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆65Updated 3 years ago
• maestro-project / confuciux
  ☆31Updated 3 years ago
• kartik-hegde / mindmappings
  A reference implementation of the Mind Mappings Framework.
  ☆28Updated 2 years ago
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆46Updated 2 weeks ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆32Updated last year
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 4 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆40Updated last week
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆39Updated 2 years ago
• awai54st / Logic-Shrinkage
  ☆20Updated 2 years ago
• KULeuven-MICAS / zigzag-imc
  HW accelerator mapping optimization framework for in-memory computing
  ☆19Updated 2 months ago
• gicLAB / SECDA
  ☆18Updated last year
• alexmr09 / Mixed-precision-Neural-Networks-on-RISC-V-Cores
  ☆13Updated 3 months ago
• sfu-arch / SpGEMM
  ☆33Updated 3 years ago
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆91Updated 4 years ago
• isakedo / DNNsim
  ☆30Updated 4 years ago
• maestro-project / magma
  ☆16Updated 2 years ago