Alternatives and similar repositories for systolic-array-dataflow-optimizer

Users that are interested in systolic-array-dataflow-optimizer are comparing it to the libraries listed below

• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆48Updated 7 months ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆66Updated 4 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆47Updated 3 years ago
• GATECH-EIC / DNN-Chip-Predictor
  [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…
  ☆25Updated 3 years ago
• GATECH-EIC / AutoDNNchip
  ☆71Updated 5 years ago
• isakedo / DNNsim
  ☆35Updated 5 years ago
• CRAFT-THU / XB-Sim
  A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration
  ☆35Updated 3 years ago
• Accelergy-Project / processing-in-memory-design
  ☆25Updated last year
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆58Updated last week
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆67Updated last month
• Sibylau / HLS_designs
  Systolic array implementations for Cholesky, LU, and QR decomposition
  ☆46Updated 11 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆81Updated 3 years ago
• neurosim / DNN_NeuroSim_V1.1
  Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)
  ☆22Updated 4 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆35Updated 6 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 5 years ago
• sharc-lab / DGNN-Booster
  ☆15Updated 2 years ago
• lukasc-ch / ExtendedBitPlaneCompression
  Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…
  ☆19Updated 6 years ago
• hyoukjun / DesignCNNAccelerators
  Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017
  ☆31Updated 7 years ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆40Updated 2 years ago
• fffasttime / AnyPackingNet
  ☆29Updated 6 months ago
• NeuraChip / neurachip
  NeuraChip Accelerator Simulator
  ☆14Updated last year
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆21Updated 2 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆86Updated last year
• CASR-HKU / DPACS
  ☆18Updated 2 years ago
• yonseicasl / NeuroSpector
  NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators
  ☆21Updated 7 months ago
• maestro-project / gamma-timeloop
  ☆15Updated last year
• pku-liang / TensorLib
  A Spatial Accelerator Generation Framework for Tensor Algebra.
  ☆60Updated 3 years ago
• georgia-tech-synergy-lab / hardtaco-hls
  HLS project modeling various sparse accelerators.
  ☆12Updated 3 years ago
• kartik-hegde / mindmappings
  A reference implementation of the Mind Mappings Framework.
  ☆30Updated 3 years ago