suhasr1991 / Convolutional-Neural-Network-hardware-using-VerilogLinks
A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. This layer takes input from a memory. A MATLAB script was created to get the floating point inputs and convert it to 7 bit signed binary output. This was done for inputs as well as the weights in these two layers.…
☆18Updated 7 years ago
Alternatives and similar repositories for Convolutional-Neural-Network-hardware-using-Verilog
Users that are interested in Convolutional-Neural-Network-hardware-using-Verilog are comparing it to the libraries listed below
Sorting:
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- A systolic array matrix multiplier☆25Updated 6 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- ☆68Updated 6 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- SRAM☆22Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated this week
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆35Updated 5 years ago
- ☆36Updated 6 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- This is a tutorial on standard digital design flow☆79Updated 4 years ago
- General Purpose AXI Direct Memory Access☆59Updated last year
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆35Updated 3 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆31Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆17Updated 4 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆12Updated last year
- CNN accelerator☆27Updated 8 years ago
- ☆27Updated 5 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆25Updated 7 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆20Updated last month
- ☆44Updated last year
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆59Updated last year
- HLS for Networks-on-Chip☆36Updated 4 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆27Updated 6 years ago
- SoC Based on ARM Cortex-M3☆33Updated 4 months ago