suhasr1991 / Convolutional-Neural-Network-hardware-using-VerilogLinks
A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. This layer takes input from a memory. A MATLAB script was created to get the floating point inputs and convert it to 7 bit signed binary output. This was done for inputs as well as the weights in these two layers.…
☆18Updated 7 years ago
Alternatives and similar repositories for Convolutional-Neural-Network-hardware-using-Verilog
Users that are interested in Convolutional-Neural-Network-hardware-using-Verilog are comparing it to the libraries listed below
Sorting:
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- A verilog implementation for Network-on-Chip☆79Updated 7 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 8 years ago
- The Verilog source code for DRUM approximate multiplier.☆32Updated 2 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆74Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆34Updated 5 years ago
- A systolic array matrix multiplier☆30Updated 6 years ago
- CNN accelerator☆28Updated 8 years ago
- ☆40Updated 6 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆78Updated last month
- MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement☆13Updated 3 years ago
- ☆72Updated 7 years ago
- ☆25Updated last year
- Systolic array based simple TPU for CNN on PYNQ-Z2☆40Updated 3 years ago
- A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…☆18Updated 2 years ago
- ☆14Updated 2 years ago
- ☆29Updated 6 years ago
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated last month
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Updated 4 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Updated last month
- SRAM☆22Updated 5 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- HLS for Networks-on-Chip☆39Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 3 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆33Updated 4 years ago
- The memory model was leveraged from micron.☆26Updated 7 years ago