mohsaied / rtl2booksimLinks
Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.
☆22Updated 10 years ago
Alternatives and similar repositories for rtl2booksim
Users that are interested in rtl2booksim are comparing it to the libraries listed below
Sorting:
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- cycle accurate Network-on-Chip Simulator☆31Updated 2 years ago
- ☆27Updated 6 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆53Updated 8 years ago
- HLS for Networks-on-Chip☆37Updated 4 years ago
- Ratatoskr NoC Simulator☆28Updated 4 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Updated 12 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆44Updated 10 months ago
- ☆18Updated last month
- ☆31Updated 5 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆43Updated 8 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆64Updated last week
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- Development of a Network on Chip Simulation using SystemC.☆33Updated 8 years ago
- The official NaplesPU hardware code repository☆19Updated 6 years ago
- Public release☆57Updated 6 years ago
- ☆28Updated last year
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- ☆78Updated 11 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆31Updated 7 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆29Updated this week
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Updated 7 years ago
- Project repo for the POSH on-chip network generator☆52Updated 7 months ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Updated 5 years ago
- Extending BookSim2.0 and HotSpot6.0 for Power, Performance and Thermal evaluation of 3D NoC Architectures☆10Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- ☆39Updated last year
- ☆36Updated 7 months ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆25Updated 3 years ago