Dazhuzhu-github / systolic-arrayLinks
verilog实现TPU中的脉动阵列计算卷积的module
☆154Updated 8 months ago
Alternatives and similar repositories for systolic-array
Users that are interested in systolic-array are comparing it to the libraries listed below
Sorting:
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆179Updated 6 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆131Updated 6 months ago
- ☆124Updated 5 years ago
- ☆46Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆242Updated 2 years ago
- IC implementation of Systolic Array for TPU☆329Updated last year
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆227Updated last year
- Deep Learning Accelerator (Convolution Neural Networks)☆197Updated 8 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆114Updated 5 years ago
- verilog实现systolic array及配套IO☆11Updated last year
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆122Updated last year
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Updated 4 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆47Updated 3 years ago
- General CNN_Accelerator design.卷积神经网络加 速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆88Updated 10 months ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆22Updated last year
- IC implementation of TPU☆146Updated 6 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆41Updated 3 years ago
- 3×3脉动阵列乘法器☆50Updated 6 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆67Updated 7 years ago
- Convolutional Neural Network RTL-level Design☆74Updated 4 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆41Updated last year
- CPU Design Based on RISCV ISA☆129Updated last year
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆220Updated 3 months ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆40Updated last year
- Hardware accelerator for convolutional neural networks☆64Updated 3 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆180Updated last year
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆65Updated last year
- ☆14Updated 2 years ago
- ☆10Updated 4 years ago
- Verilog implementation of Softmax function☆78Updated 3 years ago