shehanmunasinghe / tinyGPULinks
tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog
☆48Updated 4 years ago
Alternatives and similar repositories for tinyGPU
Users that are interested in tinyGPU are comparing it to the libraries listed below
Sorting:
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆40Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆63Updated 6 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- DDR4 Simulation Project in System Verilog☆42Updated 10 years ago
- ☆32Updated 2 weeks ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆35Updated last year
- ☆73Updated this week
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆107Updated 2 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated 2 months ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- Learn NVDLA by SOMNIA☆36Updated 5 years ago
- The multi-core cluster of a PULP system.☆105Updated this week
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- ☆47Updated 3 months ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 9 months ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆59Updated 8 months ago
- FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.☆59Updated 7 months ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- Wraps the NVDLA project for Chipyard integration☆21Updated 4 months ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated 11 months ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Updated last year
- The official NaplesPU hardware code repository☆17Updated 6 years ago
- Simple runtime for Pulp platforms☆48Updated 2 weeks ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆26Updated last month
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆41Updated last year
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆40Updated 2 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆38Updated 3 years ago
- A RISC-V Core (RV32I) written in Chisel HDL☆103Updated 4 months ago