AI Chip project
☆34Jul 14, 2021Updated 5 years ago
Alternatives and similar repositories for TPU
Users that are interested in TPU are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- AIChip 2021 project, NCKU☆18May 6, 2021Updated 5 years ago
- ☆55Jan 14, 2021Updated 5 years ago
- IC implementation of TPU☆156Dec 18, 2019Updated 6 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆174May 10, 2025Updated last year
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 5 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Template for project1 TPU☆23May 1, 2021Updated 5 years ago
- Small-scale Tensor Processing Unit built on an FPGA☆228Aug 4, 2019Updated 6 years ago
- Tensor Processing Unit implementation in Verilog☆14Mar 18, 2025Updated last year
- ☆16Apr 24, 2023Updated 3 years ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆177Jun 9, 2023Updated 3 years ago
- Antmicro's open hardware baseboard for the Google Coral i.MX8 + Edge TPU SoM☆81Aug 7, 2023Updated 2 years ago
- IC implementation of Systolic Array for TPU☆367Oct 21, 2024Updated last year
- A FPGA Based CNN accelerator, following Google's TPU V1.☆174Jul 25, 2019Updated 7 years ago
- Implementation of a Tensor Processing Unit for embedded systems and the IoT.☆571Jan 5, 2019Updated 7 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…☆273May 6, 2023Updated 3 years ago
- 本项目是一个基于RISC-V指令集架构的向量处理器(Vector Processing Unit, VPU)设计,旨在实现RISC-V向量扩展(RVV)规范中定义的向量运算功能。涵盖了处理器设计、计算机体系结构和硬件描述语言编程等多个领域的知识。☆20May 8, 2025Updated last year
- Special Function Units (SFUs) are hardware accelerators, their implementation helps improve the performance of GPUs to process some of th…☆17Sep 21, 2025Updated 10 months ago
- ☆11Apr 29, 2022Updated 4 years ago
- 大三上做的本科毕设,包含BNN的替代梯度训练,verilog电路实现,完成180nm工艺流片。☆26Jun 30, 2025Updated last year
- SystemVerilog Implementations of CUDA/TensorCore/TPU GEMM Operations☆22Apr 12, 2026Updated 3 months ago
- Superscalar Out-of-Order NPU Design on FPGA☆15May 17, 2024Updated 2 years ago
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- SRAM Design using OpenSource Applications☆25Jul 16, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor☆20Updated this week
- ☆97Nov 12, 2025Updated 8 months ago
- ☆10Dec 15, 2023Updated 2 years ago
- This is a simple Risc-v core for software simulation on FPGA.☆10Apr 9, 2022Updated 4 years ago
- a student trainning project for HLS and transformer☆11Oct 19, 2022Updated 3 years ago
- ☆40Jun 9, 2022Updated 4 years ago
- An out-of-order processor that supports multiple instruction sets.☆23Aug 23, 2022Updated 3 years ago
- Minimal FPGA hardware/software co-design demo with UART protocol, scratchpad memory, and an int8 dot-product accelerator, plus Python/C++…☆28May 12, 2026Updated 2 months ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆34Mar 13, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Physical Downlink Shared Channel (PDSCH) in 5G New Radio.☆12Jan 29, 2024Updated 2 years ago
- 基于玄铁openc906,搭建最小化SoC系统☆21Apr 7, 2025Updated last year
- A simple automatic parking system for car based on fuzzy logics by matlab.☆13Apr 26, 2017Updated 9 years ago
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 6 years ago
- [SIGMETRICS 2022] One Proxy Device Is Enough for Hardware-Aware Neural Architecture Search☆13Nov 3, 2021Updated 4 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆34May 17, 2026Updated 2 months ago
- OV7670 Camera Module Initialize with XILINX ZYNQ Driver☆12Oct 22, 2016Updated 9 years ago