AI Chip project
☆34Jul 14, 2021Updated 4 years ago
Alternatives and similar repositories for TPU
Users that are interested in TPU are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- AIChip 2021 project, NCKU☆18May 6, 2021Updated 5 years ago
- ☆53Jan 14, 2021Updated 5 years ago
- IC implementation of TPU☆153Dec 18, 2019Updated 6 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆167May 10, 2025Updated 11 months ago
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Template for project1 TPU☆23May 1, 2021Updated 5 years ago
- Small-scale Tensor Processing Unit built on an FPGA☆221Aug 4, 2019Updated 6 years ago
- Tensor Processing Unit implementation in Verilog☆14Mar 18, 2025Updated last year
- ☆16Apr 24, 2023Updated 3 years ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆175Jun 9, 2023Updated 2 years ago
- Antmicro's open hardware baseboard for the Google Coral i.MX8 + Edge TPU SoM☆80Aug 7, 2023Updated 2 years ago
- IC implementation of Systolic Array for TPU☆353Oct 21, 2024Updated last year
- A FPGA Based CNN accelerator, following Google's TPU V1.☆175Jul 25, 2019Updated 6 years ago
- Implementation of a Tensor Processing Unit for embedded systems and the IoT.☆560Jan 5, 2019Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…☆270May 6, 2023Updated 3 years ago
- RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor☆18Apr 8, 2026Updated 3 weeks ago
- ☆35Jun 9, 2022Updated 3 years ago
- ☆11Apr 29, 2022Updated 4 years ago
- Superscalar Out-of-Order NPU Design on FPGA☆14May 17, 2024Updated last year
- ☆89Apr 10, 2026Updated 3 weeks ago
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆29Mar 13, 2025Updated last year
- SRAM Design using OpenSource Applications☆24Jul 16, 2021Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆10Dec 15, 2023Updated 2 years ago
- ☆102Mar 5, 2026Updated 2 months ago
- An out-of-order processor that supports multiple instruction sets.☆22Aug 23, 2022Updated 3 years ago
- This is a simple Risc-v core for software simulation on FPGA.☆10Apr 9, 2022Updated 4 years ago
- a student trainning project for HLS and transformer☆11Oct 19, 2022Updated 3 years ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆97Apr 25, 2026Updated last week
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆18Aug 27, 2025Updated 8 months ago
- COMS 超大规模集成电路设计书籍☆32May 12, 2022Updated 3 years ago
- [SIGMETRICS 2022] One Proxy Device Is Enough for Hardware-Aware Neural Architecture Search☆13Nov 3, 2021Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- 大三上做的本科毕设,包含BNN的替代梯度训练,verilog电路实现,完成180nm工艺流片。☆24Jun 30, 2025Updated 10 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆33Updated this week
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 6 years ago
- ☆15Mar 9, 2026Updated last month
- 记录阅读各类paper的想法笔记(关注体系结构,机器学习系统,深度学习,计算机视觉)☆25Oct 25, 2019Updated 6 years ago
- Transfer data from DDR memory to AXI4-Stream Data FIFO and back through AXI DMA☆23May 20, 2019Updated 6 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago