abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-ProcessorLinks
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be …
☆46Updated last year
Alternatives and similar repositories for Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
Users that are interested in Design-and-ASIC-Implementation-of-32-Point-FFT-Processor are comparing it to the libraries listed below
Sorting:
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆66Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆75Updated last year
- General Purpose AXI Direct Memory Access☆57Updated last year
- PCIE 5.0 Graduation project (Verification Team)☆79Updated last year
- Implementing Different Adder Structures in Verilog☆71Updated 5 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆62Updated last year
- ☆16Updated last year
- RTL Verilog library for various DSP modules☆89Updated 3 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆49Updated 6 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆74Updated 4 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆110Updated 3 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆60Updated last year
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆70Updated 4 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆90Updated 6 years ago
- AXI Interconnect☆52Updated 4 years ago
- ☆60Updated 2 years ago
- This is the repository for the IEEE version of the book☆70Updated 4 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆35Updated 2 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆31Updated last year
- AXI4 BFM in Verilog☆32Updated 8 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆24Updated 2 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆20Updated last year
- ☆47Updated 4 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆65Updated last year
- Asynchronous fifo in verilog☆35Updated 9 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆20Updated last year