dldldlfma / super_small_toy_tpuView external linksLinks
☆49Jan 14, 2021Updated 5 years ago
Alternatives and similar repositories for super_small_toy_tpu
Users that are interested in super_small_toy_tpu are comparing it to the libraries listed below
Sorting:
- AI Chip project☆34Jul 14, 2021Updated 4 years ago
- AIChip 2021 project, NCKU☆17May 6, 2021Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆159May 10, 2025Updated 9 months ago
- IC implementation of TPU☆147Dec 18, 2019Updated 6 years ago
- Small-scale Tensor Processing Unit built on an FPGA☆218Aug 4, 2019Updated 6 years ago
- ☆12Apr 16, 2022Updated 3 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆172Jul 25, 2019Updated 6 years ago
- Template for project1 TPU☆23May 1, 2021Updated 4 years ago
- Implementation of a Tensor Processing Unit for embedded systems and the IoT.☆542Jan 5, 2019Updated 7 years ago
- IC implementation of Systolic Array for TPU☆333Oct 21, 2024Updated last year
- Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…☆273May 6, 2023Updated 2 years ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆170Jun 9, 2023Updated 2 years ago
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 4 years ago
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated 10 months ago
- SNN on FPGA☆12Apr 26, 2022Updated 3 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 9 years ago
- A nest brain simulator based on FPGA(LIF NEURON)☆15Dec 14, 2021Updated 4 years ago
- bitfusion verilog implementation☆12Feb 21, 2022Updated 3 years ago
- Verilog Sigmoid and Tanh functions which can be configured and added to your neural network project☆16Mar 9, 2020Updated 5 years ago
- [ASP-DAC 2025] "NeuronQuant: Accurate and Efficient Post-Training Quantization for Spiking Neural Networks" Official Implementation☆15Mar 6, 2025Updated 11 months ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆17Feb 27, 2021Updated 4 years ago
- ES-203 Computer Organization & Architecture CNN on FPGA board☆17Feb 23, 2022Updated 3 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Mar 5, 2018Updated 7 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆27Jul 4, 2019Updated 6 years ago
- ☆20Apr 7, 2021Updated 4 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆32Aug 13, 2024Updated last year
- 3×3脉动阵列乘法器☆50Sep 18, 2019Updated 6 years ago
- An automated HDC platform☆11Updated this week
- This repository contains full code of Softmax Layer in Verilog☆21Jul 29, 2020Updated 5 years ago
- COMS 超大规模集成电路设计书籍☆31May 12, 2022Updated 3 years ago
- ☆48Aug 23, 2021Updated 4 years ago
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 6 years ago
- IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures☆29Jul 7, 2019Updated 6 years ago
- I will share some useful or interesting papers about neuromorphic processor☆28Feb 6, 2025Updated last year
- ☆100Mar 18, 2020Updated 5 years ago
- ☆59Feb 29, 2024Updated last year
- ☆35Jun 9, 2022Updated 3 years ago
- Systolic-array based Deep Learning Accelerator generator☆28Dec 11, 2020Updated 5 years ago
- Python code to show how a systolic array works. Written for https://medium.com/@antonpaquin/whats-inside-a-tpu-c013eb51973e☆29Jun 8, 2018Updated 7 years ago