A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.
☆32Aug 28, 2025Updated 6 months ago
Alternatives and similar repositories for SystolicArray
Users that are interested in SystolicArray are comparing it to the libraries listed below
Sorting:
- a student trainning project for HLS and transformer☆11Oct 19, 2022Updated 3 years ago
- c++ version of ViT☆12Nov 13, 2022Updated 3 years ago
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆18Aug 27, 2025Updated 6 months ago
- C++ code for HLS FPGA implementation of transformer☆22Sep 11, 2024Updated last year
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabili…☆14Aug 28, 2025Updated 6 months ago
- IC implementation of Systolic Array for TPU☆343Oct 21, 2024Updated last year
- ☆27Mar 19, 2021Updated 5 years ago
- ☆12Sep 18, 2024Updated last year
- [DATE'2025, TCAD'2025] Terafly : A Multi-Node FPGA Based Accelerator Design for Efficient Cooperative Inference in LLMs☆29Nov 13, 2025Updated 4 months ago
- ☆27Jan 22, 2023Updated 3 years ago
- RapidLayout: Fast Hard Block Placement of FPGA-Optimized Systolic Arrays using Evolutionary Algorithms☆18Nov 26, 2020Updated 5 years ago
- ☆15Aug 10, 2023Updated 2 years ago
- FPGA Labs for EECS 151/251A (Fall 2021)☆11Oct 20, 2021Updated 4 years ago
- A simulation framework for modeling efficiency of Graph Neural Network Dataflows☆23Feb 14, 2025Updated last year
- A docker image for One Student One Chip's debug exam☆10Sep 22, 2023Updated 2 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Aug 26, 2023Updated 2 years ago
- A minimalist implementation of the ViT (Vision Transformer) model, using tinygrad☆15Sep 2, 2024Updated last year
- FPGA based Vision Transformer accelerator (Harvard CS205)☆152Feb 11, 2025Updated last year
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆171Jun 9, 2023Updated 2 years ago
- Library for modelling performance costs of different Neural Network workloads on NPU devices☆34Mar 11, 2026Updated last week
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Dec 10, 2022Updated 3 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆32Mar 4, 2026Updated 2 weeks ago
- An FPGA Accelerator for Transformer Inference☆93Apr 29, 2022Updated 3 years ago
- IC implementation of TPU☆148Dec 18, 2019Updated 6 years ago
- LLMA = LLM + Arithmetic coder, which use LLM to do insane text data compression. LLMA=大模型+算术编码，它能使用LLM对文本数据进行暴力的压缩，达到极高的压缩率。☆22Nov 24, 2024Updated last year
- ☆72Feb 16, 2023Updated 3 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆376Jan 20, 2025Updated last year
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆34Aug 13, 2024Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Sep 24, 2021Updated 4 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆50Jan 2, 2025Updated last year
- verilog实现TPU中的脉动阵列计算卷积的module☆164May 10, 2025Updated 10 months ago
- C++ RTL simulator for EIE(https://arxiv.org/abs/1602.01528)☆24Mar 17, 2021Updated 5 years ago
- FPGA implementation of an Apple//e (enhanced)☆16Mar 14, 2025Updated last year
- A small Neural Network Processor for Edge devices.☆18Nov 22, 2022Updated 3 years ago
- DUTH RISC-V Microprocessor☆25Dec 4, 2024Updated last year
- 给NEMU移植Linux Kernel!☆22Jun 1, 2025Updated 9 months ago
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 6 years ago
- Fault Injection Automatic Test Equipment☆16Nov 22, 2021Updated 4 years ago
- APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS☆28Mar 9, 2023Updated 3 years ago