SuperLiaoXH / SystolicArray-2D-FP16Links
基于FP16的二维脉动阵列电路设计
☆11Updated 2 years ago
Alternatives and similar repositories for SystolicArray-2D-FP16
Users that are interested in SystolicArray-2D-FP16 are comparing it to the libraries listed below
Sorting:
- eyeriss-chisel3☆41Updated 3 years ago
- ☆17Updated 2 months ago
- verilog实现TPU中的脉动阵列计算卷积的module☆124Updated 2 months ago
- Hardware accelerator for convolutional neural networks☆47Updated 2 years ago
- ☆30Updated last month
- ☆113Updated 4 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆83Updated 4 months ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆163Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- Open-source of MSD framework☆16Updated last year
- Verilog implementation of Softmax function☆67Updated 2 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆34Updated 4 years ago
- ☆34Updated 6 years ago
- ☆65Updated 6 years ago
- RTL generator for SpGEMM☆12Updated 4 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆75Updated 5 months ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆38Updated last year
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆18Updated 6 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆51Updated 9 months ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆33Updated 3 years ago
- (Verilog) A simple convolution layer implementation with systolic array structure☆13Updated 3 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- ☆41Updated 4 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆28Updated 4 years ago
- An FPGA Accelerator for Transformer Inference☆85Updated 3 years ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- Template for project1 TPU☆19Updated 4 years ago