hsiehong / tpuLinks
AIChip 2021 project, NCKU
☆18Updated 4 years ago
Alternatives and similar repositories for tpu
Users that are interested in tpu are comparing it to the libraries listed below
Sorting:
- ☆65Updated 6 years ago
- ☆41Updated 4 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- AI Chip project☆32Updated 4 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- ☆14Updated 2 years ago
- IC implementation of TPU☆127Updated 5 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆76Updated last year
- verilog实现TPU中的脉动阵列计算卷积的module☆124Updated 2 months ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆28Updated 4 years ago
- ☆34Updated 6 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Updated 4 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 6 years ago
- A verilog implementation for Network-on-Chip☆74Updated 7 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆34Updated 3 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- DDR3 function verification environment in UVM☆25Updated 7 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 7 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆163Updated 5 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆65Updated 5 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆217Updated 2 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆83Updated 4 months ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆37Updated 8 years ago