merledu / magma-si
Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL
☆11Updated last year
Alternatives and similar repositories for magma-si
Users that are interested in magma-si are comparing it to the libraries listed below
Sorting:
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- Wraps the NVDLA project for Chipyard integration☆20Updated last month
- M-extension for RISC-V cores.☆30Updated 5 months ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. Work in Progress.☆12Updated 6 months ago
- ☆11Updated 4 years ago
- SRAM☆8Updated 4 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆37Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆57Updated 3 months ago
- Virtualized Accelerator Orchestration for Multi-Tenant Workloads☆15Updated 6 months ago
- ☆18Updated last month
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆16Updated 2 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆26Updated 5 years ago
- The official NaplesPU hardware code repository☆16Updated 5 years ago
- AXI X-Bar☆19Updated 5 years ago
- ☆12Updated 8 months ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Updated 3 months ago
- RTL blocks compatible with the Rocket Chip Generator☆16Updated last month
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Updated last year
- SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.☆11Updated 4 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated this week
- ☆12Updated 2 months ago
- Network on Chip for MPSoC☆26Updated this week
- Wrapper for ETH Ariane Core☆20Updated 2 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆23Updated last week
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆36Updated last week
- A fault-injection framework using Chisel and FIRRTL☆36Updated last week
- ☆27Updated last month