merledu / magma-si
Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL
☆10Updated 10 months ago
Alternatives and similar repositories for magma-si:
Users that are interested in magma-si are comparing it to the libraries listed below
- ☆14Updated 3 weeks ago
- Wraps the NVDLA project for Chipyard integration☆19Updated 10 months ago
- cycle accurate Network-on-Chip Simulator☆25Updated last year
- A static dataflow CGRA with dynamic dataflow execution capability☆10Updated 3 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆22Updated 3 months ago
- Fast Floating Point Operators for High Level Synthesis☆20Updated last year
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆51Updated 4 years ago
- ☆33Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆33Updated 2 years ago
- ☆40Updated 5 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆42Updated last week
- ☆41Updated this week
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆27Updated 3 years ago
- Learn NVDLA by SOMNIA☆30Updated 5 years ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆15Updated 4 months ago
- HLS for Networks-on-Chip☆33Updated 3 years ago
- Network on Chip for MPSoC☆26Updated last month
- A scalable Eyeriss model in SystemC.☆24Updated 2 years ago
- ☆32Updated this week
- For contributions of Chisel IP to the chisel community.☆57Updated 2 months ago
- ☆24Updated 5 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆25Updated 3 weeks ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- Original test vector of RISC-V Vector Extension☆11Updated 3 years ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆14Updated 11 months ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆19Updated 3 months ago
- SRAM☆8Updated 4 years ago
- LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V☆23Updated 2 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆27Updated 3 months ago