merledu / magma-siLinks
Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL
☆13Updated last year
Alternatives and similar repositories for magma-si
Users that are interested in magma-si are comparing it to the libraries listed below
Sorting:
- A small Neural Network Processor for Edge devices.☆13Updated 2 years ago
- ☆27Updated 5 years ago
- Template for project1 TPU☆19Updated 4 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Updated 2 years ago
- The official NaplesPU hardware code repository☆18Updated 6 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- A scalable Eyeriss model in SystemC.☆29Updated 2 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- xkDLA：XinKai Deep Learning Accelerator (RTL)☆38Updated last year
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆10Updated 2 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆15Updated 5 months ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V☆23Updated 2 years ago
- HLS for Networks-on-Chip☆36Updated 4 years ago
- ☆18Updated 2 months ago
- ☆49Updated 5 months ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆23Updated last year
- ☆29Updated 5 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆43Updated 9 months ago
- ☆15Updated 3 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆31Updated last year
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated last week
- ☆14Updated this week
- DUTH RISC-V Superscalar Microprocessor☆31Updated 11 months ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- cycle accurate Network-on-Chip Simulator☆30Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆59Updated last year