merledu / magma-siLinks
Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL
☆13Updated last year
Alternatives and similar repositories for magma-si
Users that are interested in magma-si are comparing it to the libraries listed below
Sorting:
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆10Updated 2 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆15Updated 6 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- xkDLA：XinKai Deep Learning Accelerator (RTL)☆35Updated last year
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆21Updated last year
- A scalable Eyeriss model in SystemC.☆29Updated 2 years ago
- ☆27Updated 5 years ago
- A small Neural Network Processor for Edge devices.☆12Updated 2 years ago
- Template for project1 TPU☆19Updated 4 years ago
- The official NaplesPU hardware code repository☆18Updated 6 years ago
- A simple cycle-accurate DaDianNao simulator☆13Updated 6 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆21Updated 12 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- ☆13Updated this week
- ☆34Updated 5 months ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆30Updated last year
- ☆48Updated 4 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆58Updated 11 months ago
- ☆36Updated 4 years ago
- DMA controller for CNN accelerator☆14Updated 8 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- ☆13Updated 10 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Updated 2 years ago
- ☆18Updated last month
- cycle accurate Network-on-Chip Simulator☆30Updated 2 years ago
- Ratatoskr NoC Simulator☆27Updated 4 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆21Updated 9 years ago