sharc-lab / Edge-MoELinks
Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts
☆132Updated last year
Alternatives and similar repositories for Edge-MoE
Users that are interested in Edge-MoE are comparing it to the libraries listed below
Sorting:
- An FPGA Accelerator for Transformer Inference☆92Updated 3 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆54Updated 2 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆110Updated 11 months ago
- [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design☆125Updated 2 years ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆141Updated 10 months ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆35Updated this week
- ☆46Updated 2 years ago
- Open-source of MSD framework☆16Updated 2 years ago
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆117Updated last year
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆95Updated 4 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆20Updated 6 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆43Updated 2 years ago
- A co-design architecture on sparse attention☆54Updated 4 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 5 months ago
- Research and Materials on Hardware implementation of Transformer Model☆294Updated 10 months ago
- ☆58Updated last year
- Collection of kernel accelerators optimised for LLM execution☆25Updated last month
- A reading list for SRAM-based Compute-In-Memory (CIM) research.☆109Updated 2 months ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆219Updated last year
- ☆48Updated 4 years ago
- ☆113Updated 2 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆162Updated this week
- A collection of tutorials for the fpgaConvNet framework.☆47Updated last year
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆42Updated 4 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆73Updated 2 months ago
- ☆31Updated 9 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆69Updated 3 months ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago