Xilinx / XRTLinks
Run Time for AIE and FPGA based platforms
☆630Updated this week
Alternatives and similar repositories for XRT
Users that are interested in XRT are comparing it to the libraries listed below
Sorting:
- Vitis_Accel_Examples☆562Updated 2 months ago
- Vitis Libraries☆1,037Updated last month
- ☆732Updated 4 months ago
- Vitis In-Depth Tutorials☆1,470Updated 2 weeks ago
- ☆303Updated last week
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆330Updated 9 months ago
- Vitis HLS LLVM source code and examples☆397Updated 3 weeks ago
- SDAccel Examples☆359Updated 3 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆366Updated 9 months ago
- Implementation of a Tensor Processing Unit for embedded systems and the IoT.☆511Updated 6 years ago
- Dataflow compiler for QNN inference on FPGAs☆890Updated this week
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆862Updated 3 months ago
- ☆230Updated 2 months ago
- ☆471Updated last year
- Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous pl…☆300Updated last week
- Xilinx QDMA IP Drivers☆732Updated 2 months ago
- 100 Gbps TCP/IP stack for Vitis shells☆218Updated last year
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆385Updated last week
- Parallel Programming for FPGAs -- An open-source high-level synthesis book☆858Updated 3 weeks ago
- SystemC Reference Implementation☆610Updated last month
- AMD OpenNIC Project Overview☆288Updated 2 years ago
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆433Updated 5 years ago
- Vitis HLS Library for FINN☆208Updated 3 weeks ago
- ☆132Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆613Updated this week
- It's for SDC-AI Lecture Notes☆15Updated last year
- Xilinx Tcl Store☆368Updated 2 weeks ago
- Verilog AXI stream components for FPGA implementation☆834Updated 8 months ago
- SDAccel Development Environment Tutorials☆111Updated 5 years ago
- Build Customized FPGA Implementations for Vivado☆341Updated this week