Run Time for AIE and FPGA based platforms
☆688Oct 6, 2026Updated this week
Alternatives and similar repositories for XRT
Users that are interested in XRT are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Vitis Libraries☆1,131Sep 3, 2026Updated last month
- Vitis_Accel_Examples☆608Aug 31, 2026Updated last month
- ☆164Jan 28, 2025Updated last year
- Vitis In-Depth Tutorials☆1,623Sep 9, 2026Updated last month
- ☆141Jul 16, 2026Updated 2 months ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆111Jun 30, 2025Updated last year
- Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.☆1,806Feb 24, 2026Updated 7 months ago
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆49Jul 24, 2024Updated 2 years ago
- Introductory examples for using PYNQ with Alveo☆54Mar 14, 2023Updated 3 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆342Jan 20, 2025Updated last year
- ☆819Jul 13, 2026Updated 2 months ago
- Xilinx DMA IP Drivers☆863Aug 24, 2026Updated last month
- 100 Gbps TCP/IP stack for Vitis shells☆242Apr 23, 2024Updated 2 years ago
- Dataflow compiler for QNN inference on FPGAs☆1,079Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- For publishing the source for UG1352 "Get Moving with Alveo"☆51Jun 17, 2020Updated 6 years ago
- The official Linux kernel from Xilinx☆1,565Sep 25, 2026Updated 2 weeks ago
- Fork of LLVM to support AMD AIEngine processors☆212Oct 2, 2026Updated last week
- VNx: Vitis Network Examples☆166Aug 25, 2025Updated last year
- Python Productivity for ZYNQ☆2,369Sep 29, 2026Updated last week
- A close-to-metal Python API for programming AMD Ryzen™ AI NPUs (AI Engines), built on an open-source MLIR-based compiler toolchain.☆700Updated this week
- Build Customized FPGA Implementations for Vivado☆391Oct 2, 2026Updated last week
- Vitis HLS Library for FINN☆229Updated this week
- SDAccel Development Environment Tutorials☆110Apr 8, 2020Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Vitis HLS LLVM source code and examples☆417Aug 4, 2026Updated 2 months ago
- SDAccel Examples☆361May 20, 2022Updated 4 years ago
- XRM (Xilinx FPGA Resource Manager) Document:☆27Nov 13, 2023Updated 2 years ago
- Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous pl…☆458Updated this week
- DPU on PYNQ☆249Aug 12, 2025Updated last year
- Parallel Programming for FPGAs -- An open-source high-level synthesis book☆913Jan 16, 2026Updated 8 months ago
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆969Aug 3, 2026Updated 2 months ago
- Dataflow QNN inference accelerator examples on FPGAs☆265Mar 10, 2026Updated 6 months ago
- Official repository of the AWS EC2 FPGA Hardware and Software Development Kit☆1,685Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- PYNQ Composabe Overlays☆81Jun 17, 2024Updated 2 years ago
- ☆339Sep 25, 2026Updated 2 weeks ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Apr 28, 2020Updated 6 years ago
- AMD XDNA Driver (amdxdna.ko) for Linux and XRT SHIM library☆620Updated this week
- ☆40Aug 11, 2023Updated 3 years ago
- A scalable High-Level Synthesis framework on MLIR☆304May 15, 2024Updated 2 years ago
- The Riallto Open Source Project from AMD☆87Apr 10, 2025Updated last year