Alternatives and similar repositories for SDAccel_Examples:

Users that are interested in SDAccel_Examples are comparing it to the libraries listed below

• Xilinx / SDAccel-Tutorials
  SDAccel Development Environment Tutorials
  ☆108Updated 4 years ago
• Xilinx / Vitis_Accel_Examples
  Vitis_Accel_Examples
  ☆531Updated last month
• spcl / gemm_hls
  Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
  ☆331Updated 2 months ago
• definelicht / hlslib
  A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
  ☆317Updated 2 months ago
• Xilinx / ml-suite
  Getting Started with Xilinx ML Suite
  ☆337Updated 4 years ago
• fpgasystems / spooNN
  FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)
  ☆265Updated 5 years ago
• nvdla / doc
  Documentation for NVDLA.
  ☆246Updated 7 months ago
• cornell-zhang / bnn-fpga
  Binarized Convolutional Neural Networks on Software-Programmable FPGAs
  ☆304Updated 4 years ago
• Xilinx / CHaiDNN
  HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs
  ☆325Updated 5 years ago
• OpenDLA / OpenDLA
  A discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.
  ☆140Updated 7 years ago
• Xilinx / SDSoC_Examples
  ☆83Updated 4 years ago
• hsharma35 / dnnweaver2
  Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.
  ☆209Updated 5 years ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆306Updated this week
• spcl / hls_tutorial_examples
  Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
  ☆199Updated 3 years ago
• Xilinx / Vitis-In-Depth-Tutorial
  ☆117Updated 3 years ago
• IBM / AccDNN
  A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
  ☆414Updated 5 years ago
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆266Updated 4 months ago
• bu-icsg / dana
  Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  ☆210Updated 5 years ago
• fpgasystems / Vitis_with_100Gbps_TCP-IP
  100 Gbps TCP/IP stack for Vitis shells
  ☆203Updated 11 months ago
• Xilinx / Vitis-HLS-Introductory-Examples
  ☆657Updated 4 months ago
• Xilinx / xfopencv
  ☆330Updated 4 years ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆191Updated last week
• fpgasystems / fpga-network-stack
  Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
  ☆800Updated last week
• cornell-zhang / rosetta
  Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
  ☆165Updated last year
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆407Updated 6 years ago
• changwoolee / lenet5_hls
  FPGA Accelerator for CNN using Vivado HLS
  ☆312Updated 3 years ago
• mtmd / FPGA_Based_CNN
  FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.
  ☆179Updated 8 years ago
• Xilinx / XRT
  Run Time for AIE and FPGA based platforms
  ☆579Updated this week
• Xilinx / SDSoC-Tutorials
  SDSoC™ (Software-Defined System-On-Chip) Environment Tutorials
  ☆149Updated 5 years ago
• fpgadeveloper / fpga-drive-aximm-pcie
  Example designs for FPGA Drive FMC
  ☆238Updated 2 months ago