UCLA-VAST / hbmbench
☆23Updated 4 years ago
Alternatives and similar repositories for hbmbench:
Users that are interested in hbmbench are comparing it to the libraries listed below
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Updated last year
- ☆25Updated 3 years ago
- ☆29Updated 6 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- ☆10Updated 2 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆53Updated 3 years ago
- ☆26Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆90Updated 7 months ago
- ☆35Updated 4 years ago
- Stencil with Optimized Dataflow Architecture Compiler☆16Updated 5 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆29Updated 6 years ago
- STONNE Simulator integrated into SST Simulator☆19Updated last year
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago
- EQueue Dialect☆40Updated 3 years ago
- ☆13Updated last year
- ☆50Updated last month
- A Scalable BFS Accelerator on FPGA-HBM Platform☆13Updated 3 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- ☆16Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆71Updated 6 years ago
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆18Updated 5 years ago
- Processing in Memory Emulation☆20Updated 2 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆56Updated 3 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆64Updated 10 months ago
- ☆71Updated 2 years ago
- A graph linear algebra overlay☆51Updated 2 years ago