UCLA-VAST / hbmbench
☆23Updated 4 years ago
Alternatives and similar repositories for hbmbench:
Users that are interested in hbmbench are comparing it to the libraries listed below
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Updated last year
- ☆25Updated 3 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆69Updated 5 years ago
- ☆47Updated last month
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- ☆9Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- ☆57Updated last year
- ☆27Updated 5 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆70Updated 3 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- ☆71Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆87Updated 5 months ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆53Updated 3 years ago
- ☆11Updated last year
- MAESTRO binary release☆22Updated 5 years ago
- Public repostory for the DAC 2021 paper "Scaling up HBM Efficiency of Top-K SpMV forApproximate Embedding Similarity on FPGAs"☆14Updated 3 years ago
- Stencil with Optimized Dataflow Architecture Compiler☆16Updated 4 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆77Updated 7 months ago
- MAERI public release☆31Updated 3 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- ☆15Updated 2 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆62Updated last year
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆20Updated 4 months ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 2 years ago
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year