UCLA-VAST / hbmbench
☆23Updated 4 years ago
Alternatives and similar repositories for hbmbench:
Users that are interested in hbmbench are comparing it to the libraries listed below
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- ☆9Updated 2 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Updated 11 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆68Updated 3 years ago
- ☆11Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆84Updated 4 months ago
- ☆25Updated 3 years ago
- ☆34Updated 3 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 3 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆52Updated 3 years ago
- Stencil with Optimized Dataflow Architecture Compiler☆16Updated 4 years ago
- ☆71Updated 2 years ago
- Template-based Reconfigurable Architecture Modeling Framework☆13Updated 2 years ago
- ☆27Updated 5 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆44Updated 2 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆66Updated 5 years ago
- ☆42Updated 10 months ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 5 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆60Updated 3 years ago
- ☆14Updated 2 years ago
- CGRA framework with vectorization support.☆24Updated this week
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆41Updated 7 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆41Updated this week
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 2 years ago
- ☆15Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- ☆57Updated last year
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆48Updated 7 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆60Updated 7 months ago