UCLA-VAST / hbmbench
☆23Updated 4 years ago
Alternatives and similar repositories for hbmbench:
Users that are interested in hbmbench are comparing it to the libraries listed below
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- ☆10Updated 2 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- ☆25Updated 3 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆90Updated 6 months ago
- Domain-Specific Architecture Generator 2☆20Updated 2 years ago
- ☆29Updated 5 years ago
- ☆13Updated last year
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆73Updated 3 years ago
- ☆28Updated 5 years ago
- ☆35Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- NeuraChip Accelerator Simulator☆11Updated 11 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆70Updated 5 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆44Updated 2 weeks ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆53Updated 3 years ago
- ☆48Updated 3 weeks ago
- Heterogenous ML accelerator☆18Updated 6 months ago
- ☆28Updated 4 months ago
- Stencil with Optimized Dataflow Architecture Compiler☆16Updated 4 years ago
- ☆15Updated 2 years ago
- ☆26Updated 5 months ago
- Processing in Memory Emulation☆19Updated 2 years ago
- STONNE Simulator integrated into SST Simulator☆19Updated last year
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆63Updated 9 months ago
- ☆16Updated 2 years ago