Alternatives and similar repositories for SDAccel-Tutorials

Users that are interested in SDAccel-Tutorials are comparing it to the libraries listed below

• cornell-zhang / rosetta
  Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
  ☆165Updated last year
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• Xilinx / xup_vitis_network_example
  VNx: Vitis Network Examples
  ☆149Updated 10 months ago
• UCLA-VAST / AutoBridge
  [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
  ☆122Updated 2 years ago
• Xilinx / SDSoC_Examples
  ☆84Updated 4 years ago
• Xilinx / xup_compute_acceleration
  Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
  ☆47Updated 10 months ago
• RC4ML / Shuhai
  Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…
  ☆110Updated last year
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆197Updated last week
• definelicht / hlslib
  A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
  ☆319Updated 4 months ago
• Xilinx / Vitis-In-Depth-Tutorial
  ☆119Updated 3 years ago
• hpcn-uam / 100G-fpga-network-stack-core
  This repo contains the Limago code
  ☆85Updated 3 weeks ago
• Xilinx / gemx
  Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
  ☆64Updated 5 years ago
• xupgit / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆69Updated 6 years ago
• spcl / hls_tutorial_examples
  Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
  ☆199Updated 3 years ago
• OpenCAPI / oc-accel
  OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology
  ☆68Updated 9 months ago
• Xtra-Computing / ThunderGP
  HLS-based Graph Processing Framework on FPGAs
  ☆145Updated 2 years ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆105Updated 7 years ago
• OPAE / intel-fpga-bbb
  Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  ☆104Updated 4 months ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆72Updated 11 months ago
• rapidstream-org / rapidstream-tapa
  RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.
  ☆170Updated this week
• Xilinx / HLS_arbitrary_Precision_Types
  ☆46Updated last year
• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆84Updated last year
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆126Updated 2 years ago
• Xilinx / Vitis_Embedded_Platform_Source
  ☆126Updated 6 months ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆107Updated 3 years ago
• gewuek / vitis_ai_custom_platform_flow
  This project is trying to create a base vitis platform to run with DPU
  ☆47Updated 4 years ago
• hpcn-uam / Limago
  Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
  ☆126Updated 3 years ago
• fpgasystems / Vitis_with_100Gbps_TCP-IP
  100 Gbps TCP/IP stack for Vitis shells
  ☆209Updated last year
• Xilinx / pcie_qdma_ats_example
  ☆23Updated 4 years ago
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆30Updated 5 years ago