VNx: Vitis Network Examples
☆160Aug 25, 2025Updated 9 months ago
Alternatives and similar repositories for xup_vitis_network_example
Users that are interested in xup_vitis_network_example are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 100 Gbps TCP/IP stack for Vitis shells☆234Apr 23, 2024Updated 2 years ago
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆104Jun 30, 2025Updated 11 months ago
- AMD OpenNIC Shell includes the HDL source files☆142Jan 2, 2025Updated last year
- This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multip…☆25Apr 27, 2023Updated 3 years ago
- AMD OpenNIC Project Overview☆328Dec 20, 2022Updated 3 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- This repo contains the Limago code☆93May 8, 2025Updated last year
- ☆59Jul 11, 2024Updated last year
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆927Apr 15, 2026Updated last month
- Vitis_Accel_Examples☆595Mar 30, 2026Updated 2 months ago
- RFSoC QSFP Data Offload Design with GNU Radio☆29Mar 16, 2026Updated 2 months ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆22Apr 27, 2026Updated last month
- Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous pl…☆372Jun 1, 2026Updated last week
- For publishing the source for UG1352 "Get Moving with Alveo"☆51Jun 17, 2020Updated 5 years ago
- Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack☆138Sep 11, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆49Jul 24, 2024Updated last year
- Introductory examples for using PYNQ with Alveo☆54Mar 14, 2023Updated 3 years ago
- ☆13Aug 1, 2024Updated last year
- A Scalable BFS Accelerator on FPGA-HBM Platform☆13Jul 30, 2021Updated 4 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- AMD OpenNIC driver includes the Linux kernel driver☆76Jan 3, 2025Updated last year
- corundum work on vu13p☆23Nov 10, 2023Updated 2 years ago
- Open source FPGA-based NIC and platform for in-network compute☆2,355Jul 5, 2024Updated last year
- Vitis In-Depth Tutorials☆1,579May 22, 2026Updated 2 weeks ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained. Community-maintained version with binar…☆190Mar 8, 2026Updated 3 months ago
- ☆36Jan 21, 2021Updated 5 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Feb 22, 2024Updated 2 years ago
- The Riallto Open Source Project from AMD☆86Apr 10, 2025Updated last year
- Build Customized FPGA Implementations for Vivado☆381Updated this week
- ☆53Dec 10, 2019Updated 6 years ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆118Jun 15, 2025Updated 11 months ago
- A curated list of awesome smartnic tutorials, papers and projects.☆299Oct 27, 2025Updated 7 months ago
- DPDK Drivers for AMD OpenNIC☆31Jul 20, 2023Updated 2 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Run Time for AIE and FPGA based platforms☆664Updated this week
- DeepMatch: Practical Deep Packet Inspection in the Data Plane using Network Processors☆15Dec 21, 2020Updated 5 years ago
- ☆19Sep 15, 2021Updated 4 years ago
- ☆26Sep 25, 2025Updated 8 months ago
- FlowBlaze: Stateful Packet Processing in Hardware☆72Nov 16, 2022Updated 3 years ago
- Vitis Libraries☆1,104Feb 10, 2026Updated 3 months ago
- RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.☆170Mar 20, 2025Updated last year