Xilinx / Alveo-PYNQLinks
Introductory examples for using PYNQ with Alveo
☆52Updated 2 years ago
Alternatives and similar repositories for Alveo-PYNQ
Users that are interested in Alveo-PYNQ are comparing it to the libraries listed below
Sorting:
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆48Updated last year
- Train and deploy LUT-based neural networks on FPGAs☆102Updated last year
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Updated 5 years ago
- ☆30Updated 6 years ago
- PYNQ Composabe Overlays☆73Updated last year
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- ☆24Updated 5 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 2 years ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆204Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆168Updated 2 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆71Updated 5 years ago
- FPGA version of Rodinia in HLS C/C++☆40Updated 4 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆69Updated 6 years ago
- Public release☆58Updated 6 years ago
- RISC-V ISA based 32-bit processor written in HLS☆16Updated 6 years ago
- ☆87Updated last year
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆68Updated last week
- SDAccel Development Environment Tutorials☆109Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- ☆72Updated 2 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆97Updated last week
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆71Updated last year
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 4 years ago
- ☆63Updated 5 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 6 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆113Updated 2 years ago
- Next generation CGRA generator☆116Updated this week