Introductory examples for using PYNQ with Alveo
☆54Mar 14, 2023Updated 3 years ago
Alternatives and similar repositories for Alveo-PYNQ
Users that are interested in Alveo-PYNQ are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Apr 28, 2020Updated 6 years ago
- ☆10Mar 20, 2021Updated 5 years ago
- ☆14Feb 14, 2022Updated 4 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆22Jun 30, 2026Updated last month
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆107Jun 30, 2025Updated last year
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Streaming Message Interface: High-Performance Distributed Memory Programming on Reconfigurable Hardware☆15Mar 1, 2022Updated 4 years ago
- Vitis_Accel_Examples☆604Jun 15, 2026Updated last month
- VNx: Vitis Network Examples☆163Aug 25, 2025Updated 11 months ago
- Stencil with Optimized Dataflow Architecture☆18Feb 27, 2024Updated 2 years ago
- ☆14Aug 14, 2023Updated 3 years ago
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆49Jul 24, 2024Updated 2 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Feb 17, 2021Updated 5 years ago
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Jun 29, 2022Updated 4 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Build Customized FPGA Implementations for Vivado☆383Jul 30, 2026Updated 2 weeks ago
- Model zoo for the Quantized ONNX (QONNX) model format☆15Oct 31, 2025Updated 9 months ago
- ☆74Feb 16, 2023Updated 3 years ago
- Run Time for AIE and FPGA based platforms☆680Updated this week
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Aug 26, 2024Updated last year
- HLS-based Graph Processing Framework on FPGAs☆151Oct 11, 2022Updated 3 years ago
- ☆37Jun 1, 2022Updated 4 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆62Nov 23, 2021Updated 4 years ago
- RISC-V Integration for PYNQ☆176Jul 12, 2019Updated 7 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- PYNQ Composabe Overlays☆80Jun 17, 2024Updated 2 years ago
- AMD OpenNIC Shell includes the HDL source files☆150Jan 2, 2025Updated last year
- ☆30Apr 26, 2019Updated 7 years ago
- ☆11Oct 28, 2021Updated 4 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆343Jan 20, 2025Updated last year
- Accelerating SSSP for power-law graphs using an FPGA.☆23Mar 29, 2022Updated 4 years ago
- AMD OpenNIC Project Overview☆339Dec 20, 2022Updated 3 years ago
- ☆76Feb 11, 2025Updated last year
- Try the active community-maintained version with binary releases at https://github.com/tuna/tapa . This is the UCLA publication version.☆193Updated this week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆15Apr 11, 2025Updated last year
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- Xilinx Alveo Graph Analytics Product repository☆14May 18, 2022Updated 4 years ago
- HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)☆338Apr 20, 2024Updated 2 years ago
- DASS HLS Compiler☆31Oct 4, 2023Updated 2 years ago
- 100 Gbps TCP/IP stack for Vitis shells☆239Apr 23, 2024Updated 2 years ago
- ☆35Sep 12, 2019Updated 6 years ago