Introductory examples for using PYNQ with Alveo
☆52Mar 14, 2023Updated 2 years ago
Alternatives and similar repositories for Alveo-PYNQ
Users that are interested in Alveo-PYNQ are comparing it to the libraries listed below
Sorting:
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Apr 28, 2020Updated 5 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆22Oct 7, 2025Updated 4 months ago
- ☆14Feb 14, 2022Updated 4 years ago
- Streaming Message Interface: High-Performance Distributed Memory Programming on Reconfigurable Hardware☆15Mar 1, 2022Updated 4 years ago
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆102Jun 30, 2025Updated 8 months ago
- ☆10Mar 20, 2021Updated 4 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- VNx: Vitis Network Examples☆157Aug 25, 2025Updated 6 months ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Feb 17, 2021Updated 5 years ago
- ☆13Aug 14, 2023Updated 2 years ago
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆48Jul 24, 2024Updated last year
- Build Customized FPGA Implementations for Vivado☆355Updated this week
- RISC-V Integration for PYNQ☆179Jul 12, 2019Updated 6 years ago
- Vitis_Accel_Examples☆584Dec 17, 2025Updated 2 months ago
- Xilinx Alveo Graph Analytics Product repository☆14May 18, 2022Updated 3 years ago
- Stencil with Optimized Dataflow Architecture☆18Feb 27, 2024Updated 2 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆335Jan 20, 2025Updated last year
- 100 Gbps TCP/IP stack for Vitis shells☆229Apr 23, 2024Updated last year
- HLS-based Graph Processing Framework on FPGAs☆149Oct 11, 2022Updated 3 years ago
- Run Time for AIE and FPGA based platforms☆649Updated this week
- ☆24Apr 20, 2024Updated last year
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Nov 23, 2021Updated 4 years ago
- ☆30Apr 26, 2019Updated 6 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Aug 26, 2024Updated last year
- ☆72Feb 16, 2023Updated 3 years ago
- AMD OpenNIC Shell includes the HDL source files☆136Jan 2, 2025Updated last year
- PYNQ Composabe Overlays☆75Jun 17, 2024Updated last year
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆182Aug 16, 2025Updated 6 months ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆376Jan 20, 2025Updated last year
- ☆35Sep 12, 2019Updated 6 years ago
- ☆19Sep 15, 2021Updated 4 years ago
- ☆19Dec 18, 2024Updated last year
- AMD OpenNIC Project Overview☆305Dec 20, 2022Updated 3 years ago
- HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)☆341Apr 20, 2024Updated last year
- ☆37Jun 1, 2022Updated 3 years ago
- ☆11Oct 28, 2021Updated 4 years ago
- OPAE porting to Xilinx FPGA devices.☆39Aug 5, 2020Updated 5 years ago
- AMD OpenNIC driver includes the Linux kernel driver☆73Jan 3, 2025Updated last year
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆25May 18, 2025Updated 9 months ago