SFU-HiAccel / uBench
[FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
☆30Updated 3 years ago
Alternatives and similar repositories for uBench:
Users that are interested in uBench are comparing it to the libraries listed below
- ☆23Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- ☆11Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆69Updated 5 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆53Updated 3 years ago
- ☆25Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆89Updated 5 months ago
- ☆13Updated 2 years ago
- Stencil with Optimized Dataflow Architecture Compiler☆16Updated 4 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆62Updated 8 months ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- Heterogenous ML accelerator☆17Updated 5 months ago
- ☆9Updated 2 years ago
- An Open-Source Tool for CGRA Accelerators☆59Updated 2 months ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆41Updated 7 years ago
- EQueue Dialect☆40Updated 3 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆48Updated 3 months ago
- ☆14Updated last year
- A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.☆18Updated 2 years ago
- ☆57Updated last year
- gem5 repository to study chiplet-based systems☆70Updated 5 years ago
- ☆28Updated 5 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆77Updated 7 months ago
- Benchmarks for Accelerator Design and Customized Architectures☆120Updated 4 years ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆34Updated 2 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆50Updated 2 weeks ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 2 years ago
- ☆47Updated last month