Xilinx / Get_Moving_With_AlveoLinks
For publishing the source for UG1352 "Get Moving with Alveo"
☆51Updated 5 years ago
Alternatives and similar repositories for Get_Moving_With_Alveo
Users that are interested in Get_Moving_With_Alveo are comparing it to the libraries listed below
Sorting:
- VNx: Vitis Network Examples☆151Updated last year
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆112Updated last month
- AMD OpenNIC Shell includes the HDL source files☆118Updated 7 months ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆98Updated last month
- Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous pl…☆277Updated this week
- AMD OpenNIC driver includes the Linux kernel driver☆67Updated 7 months ago
- SDAccel Development Environment Tutorials☆109Updated 5 years ago
- This repo contains the Limago code☆86Updated 2 months ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- 100 Gbps TCP/IP stack for Vitis shells☆213Updated last year
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆48Updated last year
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆104Updated 6 months ago
- Distributed Accelerator OS☆63Updated 3 years ago
- FpgaNIC is an FPGA-based Versatile 100Gb SmartNIC for GPUs [ATC 22]☆131Updated last year
- Benchmarks for Accelerator Design and Customized Architectures☆128Updated 5 years ago
- RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.☆142Updated 4 months ago
- AMD OpenNIC Project Overview☆273Updated 2 years ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆200Updated 3 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆166Updated last year
- ☆24Updated 4 years ago
- HLS-based Graph Processing Framework on FPGAs☆147Updated 2 years ago
- ☆25Updated 4 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆322Updated 6 months ago
- Fast and accurate DRAM power and energy estimation tool☆168Updated last week
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆190Updated 4 years ago
- Hands-on experience programming AI Engines using Vitis Unified Software Platform☆41Updated last year
- PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing☆103Updated 2 years ago
- Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack☆127Updated 3 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆42Updated 8 years ago