Xilinx / Get_Moving_With_Alveo
For publishing the source for UG1352 "Get Moving with Alveo"
☆47Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for Get_Moving_With_Alveo
- VNx: Vitis Network Examples☆137Updated 3 months ago
- Distributed Accelerator OS☆60Updated 2 years ago
- AMD OpenNIC driver includes the Linux kernel driver☆55Updated 8 months ago
- AMD OpenNIC Shell includes the HDL source files☆99Updated 5 months ago
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆81Updated last month
- 100 Gbps TCP/IP stack for Vitis shells☆184Updated 6 months ago
- Introductory examples for using PYNQ with Alveo☆48Updated last year
- This repo contains the Limago code☆78Updated 2 years ago
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆103Updated 4 months ago
- Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern he…☆221Updated this week
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆95Updated last year
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆46Updated 3 months ago
- SDAccel Development Environment Tutorials☆107Updated 4 years ago
- ☆22Updated 3 years ago
- RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.☆104Updated 3 weeks ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆29Updated 2 years ago
- FpgaNIC is an FPGA-based Versatile 100Gb SmartNIC for GPUs☆120Updated last year
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing☆101Updated last year
- ☆47Updated 4 months ago
- Hands-on experience programming AI Engines using Vitis Unified Software Platform☆37Updated 3 months ago
- ☆25Updated last month
- PCIe library for the Xilinx 7 series FPGAs in the Bluespec language☆72Updated 2 years ago
- ☆23Updated 3 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆41Updated 7 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆158Updated last year
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆37Updated 5 years ago
- Spector: An OpenCL FPGA Benchmark Suite☆43Updated 5 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆59Updated 3 years ago
- AMD OpenNIC Project Overview☆227Updated last year