Xilinx / AlveoLinkLinks
This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multiple Alveo cards.
☆20Updated 2 years ago
Alternatives and similar repositories for AlveoLink
Users that are interested in AlveoLink are comparing it to the libraries listed below
Sorting:
- AMD OpenNIC driver includes the Linux kernel driver☆67Updated 6 months ago
- AMD OpenNIC Shell includes the HDL source files☆117Updated 6 months ago
- corundum work on vu13p☆19Updated last year
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- Framework for FPGA-accelerated Middlebox Development☆44Updated 2 years ago
- VNx: Vitis Network Examples☆150Updated 11 months ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆26Updated 3 years ago
- Distributed Accelerator OS☆63Updated 3 years ago
- MEEP FPGA Shell project, currently supporting Alveos u280 and u55c☆14Updated last year
- This repo contains the Limago code☆86Updated 2 months ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- Verilog Content Addressable Memory Module☆107Updated 3 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆18Updated 5 years ago
- ☆24Updated 4 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- ☆61Updated 4 years ago
- BlackParrot on Zynq☆43Updated 4 months ago
- DaCH: dataflow cache for high-level synthesis.☆18Updated last year
- RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.☆139Updated 3 months ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16Updated 4 years ago
- TCAM (Ternary Content-Addressable Memory) in Verilog☆52Updated last year
- ☆24Updated 4 years ago
- Ethernet switch implementation written in Verilog☆49Updated 2 years ago
- ☆76Updated 10 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Updated last year
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- ☆16Updated 3 years ago
- Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack☆127Updated 3 years ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago