Alternatives and similar repositories for ACCL

Users that are interested in ACCL are comparing it to the libraries listed below

• Xilinx / xup_aie_training
  Hands-on experience programming AI Engines using Vitis Unified Software Platform
  ☆40Updated last year
• spcl / pspin
  PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing
  ☆104Updated 2 years ago
• Xilinx / xacc
  Heterogeneous Accelerated Computed Cluster (HACC) Resources Page
  ☆22Updated 2 months ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆82Updated 6 years ago
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆31Updated 3 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated last year
• fpgasystems / hacc
  ETHZ Heterogeneous Accelerated Compute Cluster.
  ☆38Updated 2 months ago
• Xilinx / merlin-compiler
  ☆60Updated 2 years ago
• cornell-zhang / rosetta
  Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)
  ☆168Updated 2 years ago
• PrincetonUniversity / accelerator-wall
  Repository for the tools and non-commercial data used for the "Accelerator wall" paper.
  ☆51Updated 6 years ago
• OCT-FPGA / OCT-Tutorials
  ☆35Updated last month
• CMU-SAFARI / PiDRAM
  PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …
  ☆71Updated last year
• RC4ML / Shuhai
  Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…
  ☆117Updated 5 months ago
• esl-epfl / gem5-X
  The gem5-X open source framework (based on the gem5 simulator)
  ☆42Updated 2 years ago
• sstsimulator / sst-elements
  SST Architectural Simulation Components and Libraries
  ☆108Updated this week
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆113Updated 2 years ago
• cucapra / EventQueue
  EQueue Dialect
  ☆41Updated 3 years ago
• zslwyuan / PAAS_V1.0
  PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
  ☆43Updated 4 years ago
• CMU-SAFARI / VAMPIRE
  An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …
  ☆40Updated 6 years ago
• CMU-SAFARI / GPGPUSim-Ramulator
  The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…
  ☆58Updated 6 years ago
• UCLA-VAST / hbmbench
  ☆24Updated 5 years ago
• TeCSAR-UNCC / gem5-SALAM
  ☆107Updated last year
• gthparch / HBM
  High Bandwidth Memory (HBM) timing model based on DRAMSim2
  ☆45Updated 8 years ago
• Xilinx / xup_vitis_network_example
  VNx: Vitis Network Examples
  ☆155Updated 3 months ago
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆135Updated 5 years ago
• miglopst / PIM_NDP_papers
  ☆68Updated 4 years ago
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆72Updated last year
• PolyArch / dsa-framework
  Release of stream-specialization software/hardware stack.
  ☆119Updated 2 years ago
• RC4ML / FpgaNIC
  FpgaNIC is an FPGA-based Versatile 100Gb SmartNIC for GPUs [ATC 22]
  ☆136Updated 2 years ago
• MPSLab-ASU / ccf
  CGRA Compilation Framework
  ☆88Updated 2 years ago