Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators
☆105Jun 30, 2025Updated last year
Alternatives and similar repositories for ACCL
Users that are interested in ACCL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- VNx: Vitis Network Examples☆162Aug 25, 2025Updated 10 months ago
- Ready-to-link, packaged Aurora IP on four QSFP28 lanes, providing 100Gb/s throughput, flow control and status monitoring☆18Jul 1, 2026Updated 2 weeks ago
- This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multip…☆25Apr 27, 2023Updated 3 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆22Jun 30, 2026Updated 2 weeks ago
- SYCL-based 2D Stencil Simulation Framework☆18May 3, 2026Updated 2 months ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- A research shell for Alveo V80☆41Updated this week
- 100 Gbps TCP/IP stack for Vitis shells☆238Apr 23, 2024Updated 2 years ago
- Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous pl…☆432Jul 14, 2026Updated last week
- The codebase that computed the Ninth Dedekind Number☆13Jan 18, 2026Updated 6 months ago
- ☆25May 9, 2019Updated 7 years ago
- Introductory examples for using PYNQ with Alveo☆54Mar 14, 2023Updated 3 years ago
- AMD OpenNIC Project Overview☆334Dec 20, 2022Updated 3 years ago
- Vitis HLS Library for FINN☆224May 27, 2026Updated last month
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆342Jan 20, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆49Jul 24, 2024Updated last year
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆62Nov 23, 2021Updated 4 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained. Community-maintained version with binar…☆193Mar 8, 2026Updated 4 months ago
- Run Time for AIE and FPGA based platforms☆674Updated this week
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆102Sep 27, 2024Updated last year
- HW/SW co-designed end-host RPC stack☆20Oct 28, 2021Updated 4 years ago
- An MLIR-based compiler from C/C++ to AMD-Xilinx Versal AIE☆17Aug 5, 2022Updated 3 years ago
- ☆14Feb 14, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A OpenCL-based FPGA benchmark suite for HPC☆37May 4, 2026Updated 2 months ago
- ☆15Apr 18, 2023Updated 3 years ago
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆942Jul 14, 2026Updated last week
- Dataflow QNN inference accelerator examples on FPGAs☆261Mar 10, 2026Updated 4 months ago
- ☆17Updated this week
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Aug 26, 2024Updated last year
- muSYCL, the SYCL musical!☆13Aug 25, 2024Updated last year
- Train and deploy LUT-based neural networks on FPGAs☆118Jun 12, 2024Updated 2 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Mar 29, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- FPGA acceleration of arbitrary precision floating point computations.☆41May 17, 2022Updated 4 years ago
- AMD OpenNIC Shell includes the HDL source files☆145Jan 2, 2025Updated last year
- Record MPI operations on tape☆25Dec 13, 2023Updated 2 years ago
- ☆63Aug 4, 2023Updated 2 years ago
- Vitis_Accel_Examples☆603Jun 15, 2026Updated last month
- BLAS implementation for Intel FPGA☆78Nov 18, 2020Updated 5 years ago
- ☆36Jan 21, 2021Updated 5 years ago