Xilinx / xup_compute_accelerationLinks
Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
☆48Updated last year
Alternatives and similar repositories for xup_compute_acceleration
Users that are interested in xup_compute_acceleration are comparing it to the libraries listed below
Sorting:
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆204Updated 4 years ago
- Hands-on experience programming AI Engines using Vitis Unified Software Platform☆40Updated last year
- SDAccel Development Environment Tutorials☆109Updated 5 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Updated 5 years ago
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆104Updated last year
- RISC-V ISA based 32-bit processor written in HLS☆16Updated 6 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 6 years ago
- ☆30Updated 6 years ago
- Networking Overlay on PYNQ☆50Updated 6 years ago
- FPGA version of Rodinia in HLS C/C++☆40Updated 5 years ago
- VNx: Vitis Network Examples☆156Updated 5 months ago
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆74Updated last year
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆169Updated 2 years ago
- For publishing the source for UG1352 "Get Moving with Alveo"☆50Updated 5 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆128Updated 3 years ago
- Tutorials on HLS Design☆51Updated 6 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆334Updated last year
- 100 Gbps TCP/IP stack for Vitis shells☆228Updated last year
- Train and deploy LUT-based neural networks on FPGAs☆106Updated last year
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 3 years ago
- PYNQ Composabe Overlays☆74Updated last year
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆69Updated 6 years ago
- ☆27Updated 4 years ago
- ☆88Updated 3 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆54Updated 7 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆101Updated 7 months ago