Xilinx / xup_compute_accelerationLinks
Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
☆48Updated 11 months ago
Alternatives and similar repositories for xup_compute_acceleration
Users that are interested in xup_compute_acceleration are comparing it to the libraries listed below
Sorting:
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- A floating-point matrix multiplication implemented in hardware☆31Updated 4 years ago
- ☆29Updated 6 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Hands-on experience programming AI Engines using Vitis Unified Software Platform☆40Updated 11 months ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆105Updated last year
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆95Updated last week
- RISC-V ISA based 32-bit processor written in HLS☆17Updated 5 years ago
- For publishing the source for UG1352 "Get Moving with Alveo"☆51Updated 5 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆30Updated 5 years ago
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- Algorithmic C Machine Learning Library☆23Updated 6 months ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆200Updated 3 years ago
- ☆24Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆46Updated 8 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- FPGA version of Rodinia in HLS C/C++☆38Updated 4 years ago
- ☆94Updated last year
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆67Updated 9 months ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 3 months ago
- Rodinia Benchmark Suite for OpenCL-based FPGAs☆31Updated 2 years ago
- ☆46Updated last year
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆104Updated 4 months ago
- PYNQ Composabe Overlays☆73Updated last year
- A High-Level DRAM Timing, Power and Area Exploration Tool☆28Updated 4 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago