Xilinx / xup_compute_accelerationLinks
Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
☆48Updated last year
Alternatives and similar repositories for xup_compute_acceleration
Users that are interested in xup_compute_acceleration are comparing it to the libraries listed below
Sorting:
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- SDAccel Development Environment Tutorials☆110Updated 5 years ago
- ☆30Updated 6 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆200Updated 3 years ago
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆104Updated 6 months ago
- For publishing the source for UG1352 "Get Moving with Alveo"☆50Updated 5 years ago
- VNx: Vitis Network Examples☆152Updated last year
- Hands-on experience programming AI Engines using Vitis Unified Software Platform☆41Updated last year
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆30Updated 5 years ago
- Train and deploy LUT-based neural networks on FPGAs☆97Updated last year
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆71Updated 11 months ago
- FPGA version of Rodinia in HLS C/C++☆38Updated 4 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆167Updated last year
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆69Updated 6 years ago
- ☆88Updated 2 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- 100 Gbps TCP/IP stack for Vitis shells☆217Updated last year
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆322Updated 7 months ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- Networking Overlay on PYNQ☆49Updated 6 years ago
- ☆25Updated 4 years ago
- Tutorials on HLS Design☆52Updated 5 years ago
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆97Updated last month
- Algorithmic C Machine Learning Library☆26Updated 8 months ago
- AMD OpenNIC driver includes the Linux kernel driver☆68Updated 7 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆111Updated last year
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Rodinia Benchmark Suite for OpenCL-based FPGAs☆31Updated 2 years ago