Xilinx / xup_compute_accelerationLinks
Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
☆48Updated last year
Alternatives and similar repositories for xup_compute_acceleration
Users that are interested in xup_compute_acceleration are comparing it to the libraries listed below
Sorting:
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- SDAccel Development Environment Tutorials☆110Updated 5 years ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆201Updated 3 years ago
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆104Updated 9 months ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆72Updated last year
- For publishing the source for UG1352 "Get Moving with Alveo"☆50Updated 5 years ago
- RISC-V ISA based 32-bit processor written in HLS☆16Updated 5 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- VNx: Vitis Network Examples☆154Updated 2 months ago
- ☆30Updated 6 years ago
- FPGA version of Rodinia in HLS C/C++☆40Updated 4 years ago
- ☆26Updated 4 years ago
- CAPI SNAP Framework Hardware and Software☆110Updated 4 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆126Updated 2 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆112Updated 2 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆69Updated 6 years ago
- Train and deploy LUT-based neural networks on FPGAs☆100Updated last year
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Updated 5 years ago
- Tutorials on HLS Design☆52Updated 5 years ago
- Falcon Merlin Compiler☆41Updated 5 years ago
- Hands-on experience programming AI Engines using Vitis Unified Software Platform☆40Updated last year
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- Networking Overlay on PYNQ☆50Updated 6 years ago
- PYNQ Composabe Overlays☆73Updated last year
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago
- Algorithmic C Machine Learning Library☆26Updated 10 months ago
- Distributed Accelerator OS☆64Updated 3 years ago