Alternatives and similar repositories for HLS:

Users that are interested in HLS are comparing it to the libraries listed below

• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆268Updated 2 weeks ago
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆271Updated 2 weeks ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆570Updated 2 weeks ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆488Updated 2 months ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆315Updated this week
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆369Updated this week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆552Updated 3 weeks ago
• ucb-bar / berkeley-hardfloat
  ☆322Updated 7 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆614Updated this week
• Xilinx / XilinxBoardStore
  ☆286Updated last week
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆253Updated this week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆621Updated last month
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆700Updated 2 months ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆740Updated 8 months ago
• ferrandi / PandA-bambu
  PandA-bambu public repository
  ☆265Updated 2 weeks ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 5 months ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆422Updated 2 weeks ago
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆323Updated 3 years ago
• accellera-official / systemc
  SystemC Reference Implementation
  ☆548Updated last month
• phanrahan / magma
  magma circuits
  ☆260Updated 6 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆601Updated 3 years ago
• definelicht / hlslib
  A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
  ☆318Updated 3 months ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆684Updated this week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆690Updated last week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆390Updated 3 weeks ago
• pymtl / pymtl3
  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
  ☆409Updated this week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆279Updated last year
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆291Updated 2 months ago
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆120Updated 10 months ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆240Updated 6 months ago