Xilinx / HLS
Vitis HLS LLVM source code and examples
☆379Updated last month
Related projects ⓘ
Alternatives and complementary repositories for HLS
- Build Customized FPGA Implementations for Vivado☆294Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆527Updated this week
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆260Updated 3 weeks ago
- ☆290Updated 2 months ago
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆250Updated last month
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆343Updated 2 weeks ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆303Updated 7 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆438Updated last month
- Bus bridges and other odds and ends☆491Updated 10 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆230Updated this week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆379Updated this week
- ☆262Updated last week
- PandA-bambu public repository☆244Updated last month
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆206Updated this week
- Common SystemVerilog components☆521Updated this week
- Recipe for FPGA cooking☆289Updated last month
- magma circuits☆253Updated last month
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆208Updated 4 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆217Updated this week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆256Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆370Updated last week
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆389Updated 3 weeks ago
- A Linux-capable RISC-V multicore for and by the world☆627Updated this week
- Advanced Interface Bus (AIB) die-to-die hardware open source☆127Updated 2 months ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆308Updated 2 years ago
- Test suite designed to check compliance with the SystemVerilog standard.☆297Updated this week
- SystemC Reference Implementation☆496Updated 3 weeks ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆310Updated 2 years ago
- SystemRDL 2.0 language compiler front-end☆236Updated 2 months ago
- SystemC/TLM-2.0 Co-simulation framework☆222Updated 3 weeks ago