Xilinx / HLSLinks
Vitis HLS LLVM source code and examples
☆393Updated 9 months ago
Alternatives and similar repositories for HLS
Users that are interested in HLS are comparing it to the libraries listed below
Sorting:
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆276Updated 3 months ago
- Build Customized FPGA Implementations for Vivado☆330Updated this week
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆381Updated 3 weeks ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆451Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆595Updated this week
- ☆334Updated 10 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆263Updated last month
- PandA-bambu public repository☆273Updated last month
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆322Updated 6 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆516Updated 5 months ago
- ☆290Updated this week
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆281Updated 3 weeks ago
- magma circuits☆261Updated 9 months ago
- Python-based hardware modeling framework☆242Updated 5 years ago
- SystemC/TLM-2.0 Co-simulation framework☆252Updated 2 months ago
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆422Updated 3 months ago
- Bus bridges and other odds and ends☆576Updated 3 months ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆327Updated 3 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆229Updated 8 months ago
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆162Updated last month
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆285Updated 2 months ago
- Instruction Set Generator initially contributed by Futurewei☆290Updated last year
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆213Updated 5 years ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆296Updated 2 months ago
- The OpenPiton Platform☆723Updated 2 weeks ago
- SystemVerilog to Verilog conversion☆653Updated last month
- Recipe for FPGA cooking☆301Updated 10 months ago
- SystemC Reference Implementation☆585Updated 2 months ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆505Updated 8 months ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆436Updated 2 months ago