Alternatives and similar repositories for DPU-PYNQ

Users that are interested in DPU-PYNQ are comparing it to the libraries listed below

• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆208Updated last week
• Xilinx / finn-examples
  Dataflow QNN inference accelerator examples on FPGAs
  ☆232Updated last month
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆107Updated 7 years ago
• JinChen-tw / pynqz2_dpu140
  This TRD is implement DPU v1.4.0 on PYNQ-Z2 board
  ☆47Updated 5 years ago
• Xilinx / PYNQ-HelloWorld
  This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.
  ☆106Updated 2 years ago
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆88Updated 5 years ago
• Xilinx / QNN-MO-PYNQ
  ☆249Updated 4 years ago
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆157Updated 3 weeks ago
• Xilinx / Vitis_Embedded_Platform_Source
  ☆131Updated 3 months ago
• Xilinx / xup_high_level_synthesis_design_flow
  AMD University Program HLS tutorial
  ☆110Updated 11 months ago
• fpgasystems / spooNN
  FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)
  ☆280Updated 5 years ago
• Xilinx / Vitis-In-Depth-Tutorial
  ☆117Updated 4 years ago
• gewuek / vitis_ai_custom_platform_flow
  This project is trying to create a base vitis platform to run with DPU
  ☆48Updated 5 years ago
• cathalmccabe / PYNQ_tutorials
  ☆97Updated last year
• manoharvhr / PYNQ-Torch
  PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform
  ☆72Updated 5 years ago
• embedeep / FREE-TPU-V3plus-for-FPGA
  FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
  ☆158Updated 2 years ago
• zhan6841 / FPGA-Accelerator-for-AES-LeNet-VGG16
  FPGA/AES/LeNet/VGG16
  ☆108Updated 7 years ago
• cea-wind / SimpleTPU
  A FPGA Based CNN accelerator, following Google's TPU V1.
  ☆159Updated 6 years ago
• HWAC-DL / hwac_object_tracker
  FPGA accelerated TinyYOLO v2 object detection neural network
  ☆74Updated 7 years ago
• Xilinx / PYNQ-ComputerVision
  Computer Vision Overlays on Pynq
  ☆187Updated 6 years ago
• Er1cZ / Deploying_CNN_on_FPGA_using_OpenCL
  Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design con…
  ☆111Updated 7 years ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆73Updated last year
• 19801201 / SpinalHDL_CNN_Accelerator
  CNN accelerator implemented with Spinal HDL
  ☆152Updated last year
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆59Updated 3 years ago
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆163Updated last year
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆81Updated 2 years ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆227Updated 2 years ago
• spcl / gemm_hls
  Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
  ☆366Updated 8 months ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆169Updated 5 years ago
• IBM / AccDNN
  A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
  ☆430Updated 5 years ago