RC4ML / Shuhai
Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA [FCCM 20]
☆106Updated last year
Alternatives and similar repositories for Shuhai:
Users that are interested in Shuhai are comparing it to the libraries listed below
- HLS-based Graph Processing Framework on FPGAs☆145Updated 2 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆133Updated this week
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆121Updated last week
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆88Updated 6 months ago
- ☆72Updated 10 years ago
- FpgaNIC is an FPGA-based Versatile 100Gb SmartNIC for GPUs [ATC 22]☆126Updated last year
- Release of stream-specialization software/hardware stack.☆120Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆70Updated 5 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆164Updated last year
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆165Updated this week
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆70Updated 5 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- An integrated CGRA design framework☆87Updated 2 weeks ago
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆71Updated 2 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆78Updated 8 months ago
- VNx: Vitis Network Examples☆145Updated 8 months ago
- ☆23Updated 3 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆120Updated 5 years ago
- cycle accurate Network-on-Chip Simulator☆27Updated last year
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆62Updated 9 months ago
- Fast and accurate DRAM power and energy estimation tool☆152Updated this week
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆70Updated last year
- Automatic generation of FPGA-based learning accelerators for the neural network family☆63Updated 5 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- ASIC simulation of Multi-ported Memory Module. And it can offer SRAM-based dual-port basic building block to support multiple read/write …☆19Updated 8 years ago
- RTL implementation of Flex-DPE.☆98Updated 5 years ago
- RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.☆121Updated 2 weeks ago