RC4ML / ShuhaiLinks
Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA [FCCM 20]
☆118Updated 7 months ago
Alternatives and similar repositories for Shuhai
Users that are interested in Shuhai are comparing it to the libraries listed below
Sorting:
- HLS-based Graph Processing Framework on FPGAs☆149Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆177Updated 5 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆82Updated 6 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆169Updated 2 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 4 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 3 years ago
- ☆24Updated 5 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆74Updated last year
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆162Updated this week
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- ☆55Updated 7 months ago
- Release of stream-specialization software/hardware stack.☆121Updated 2 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆152Updated last week
- An integrated CGRA design framework☆91Updated 10 months ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆136Updated 5 years ago
- Automatic generation of FPGA-based learning accelerators for the neural network family☆68Updated 6 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Updated 4 years ago
- gem5 repository to study chiplet-based systems☆85Updated 6 years ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 3 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆206Updated 5 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆236Updated 3 years ago
- NVSim - A performance, energy and area estimation tool for non-volatile memory (NVM)☆132Updated 7 years ago
- Fast and accurate DRAM power and energy estimation tool☆189Updated last week
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆75Updated 3 years ago
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆210Updated 5 years ago
- ☆22Updated 2 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆72Updated 6 months ago