fastmachinelearning / hls4ml-tutorialLinks
Tutorial notebooks for hls4ml
☆366Updated last month
Alternatives and similar repositories for hls4ml-tutorial
Users that are interested in hls4ml-tutorial are comparing it to the libraries listed below
Sorting:
- Dataflow QNN inference accelerator examples on FPGAs☆231Updated 3 weeks ago
- Dataflow compiler for QNN inference on FPGAs☆868Updated this week
- DPU on PYNQ☆227Updated last month
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆363Updated 7 months ago
- Vitis HLS Library for FINN☆206Updated last month
- ☆467Updated last year
- Machine learning on FPGAs using HLS☆1,624Updated last week
- ☆450Updated last year
- ☆712Updated 2 months ago
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆431Updated 5 years ago
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆279Updated 5 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆327Updated 7 months ago
- Vitis_Accel_Examples☆558Updated last month
- ☆96Updated last year
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆201Updated 3 years ago
- Implementation of a Tensor Processing Unit for embedded systems and the IoT.☆508Updated 6 years ago
- Computer Vision Overlays on Pynq☆185Updated 5 years ago
- ☆248Updated 4 years ago
- ☆118Updated 4 years ago
- PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform☆72Updated 5 years ago
- AMD University Program HLS tutorial☆107Updated 10 months ago
- ☆224Updated last month
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆160Updated last year
- This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.☆106Updated 2 years ago
- ☆131Updated 3 months ago
- Convolutional Neural Network Using High Level Synthesis☆88Updated 4 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆30Updated 5 years ago
- Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design con…☆111Updated 7 years ago
- Implementation of CNN using Verilog☆223Updated 7 years ago