Alternatives and similar repositories for xup_high_level_synthesis_design_flow

Users that are interested in xup_high_level_synthesis_design_flow are comparing it to the libraries listed below

• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆77Updated 2 years ago
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆272Updated 10 months ago
• thousrm / universal_NPU-CNN_accelerator
  hardware design of universal NPU(CNN accelerator) for various convolution neural network
  ☆139Updated 5 months ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆129Updated 3 months ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆104Updated 4 years ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆206Updated 3 weeks ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆164Updated 5 years ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆222Updated 2 years ago
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆58Updated 4 years ago
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆128Updated 5 years ago
• gnodipac886 / ViT-FPGA-TPU
  FPGA based Vision Transformer accelerator (Harvard CS205)
  ☆127Updated 6 months ago
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆226Updated 2 weeks ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆170Updated this week
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆87Updated 4 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆95Updated last month
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆86Updated 3 months ago
• hguq / HG-PIPE
  FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
  ☆85Updated 7 months ago
• cathalmccabe / PYNQ_tutorials
  ☆95Updated last year
• bol-edu / 2022-fall-ntu
  ☆33Updated 11 months ago
• maomran / softmax
  Verilog implementation of Softmax function
  ☆67Updated 3 years ago
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆158Updated last year
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆90Updated 6 years ago
• FedericoSerafini / HLS-CNN
  High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
  ☆41Updated last year
• cameronshinn / tiny-tpu
  Small-scale Tensor Processing Unit built on an FPGA
  ☆199Updated 6 years ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆113Updated 5 years ago
• embedeep / FREE-TPU-V3plus-for-FPGA
  FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
  ☆153Updated 2 years ago
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆198Updated 5 years ago
• dldldlfma / super_small_toy_tpu
  ☆43Updated 4 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆41Updated 3 years ago
• cea-wind / SimpleTPU
  A FPGA Based CNN accelerator, following Google's TPU V1.
  ☆158Updated 6 years ago