Xilinx / xup_high_level_synthesis_design_flow
AMD University Program HLS tutorial
☆78Updated 3 months ago
Alternatives and similar repositories for xup_high_level_synthesis_design_flow:
Users that are interested in xup_high_level_synthesis_design_flow are comparing it to the libraries listed below
- verilog实现TPU中的脉动阵列计算卷积的module☆77Updated 3 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆66Updated last year
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆88Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆139Updated 5 years ago
- IC implementation of Systolic Array for TPU☆189Updated 4 months ago
- ☆100Updated 4 years ago
- Convolutional Neural Network Using High Level Synthesis☆84Updated 4 years ago
- ☆77Updated last year
- Hardware accelerator for convolutional neural networks☆36Updated 2 years ago
- ☆29Updated 5 years ago
- PYNQ Composabe Overlays☆70Updated 8 months ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆41Updated 5 months ago
- ☆29Updated 5 months ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆32Updated last month
- Convolutional accelerator kernel, target ASIC & FPGA☆181Updated last year
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆79Updated 5 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆27Updated 4 years ago
- Verilog implementation of Softmax function☆56Updated 2 years ago
- An AXI4 crossbar implementation in SystemVerilog☆131Updated 2 months ago
- ☆60Updated 6 years ago
- AMD Xilinx University Program Embedded tutorial☆32Updated 2 years ago
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆83Updated last year
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆58Updated 6 months ago
- FFT generator using Chisel☆57Updated 3 years ago
- 3×3脉动阵列乘法器☆37Updated 5 years ago
- ☆60Updated 2 years ago
- AXI总线连接器☆94Updated 4 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆173Updated 7 years ago
- Convolutional Neural Network RTL-level Design☆44Updated 3 years ago