Alternatives and similar repositories for rosetta

Users that are interested in rosetta are comparing it to the libraries listed below

• tuna / tapa
  TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.
  ☆174Updated last month
• UCLA-VAST / AutoBridge
  [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
  ☆125Updated 2 years ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆138Updated 3 months ago
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆129Updated 5 years ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆77Updated 6 years ago
• lana555 / dynamatic
  ☆87Updated last year
• UCLA-VAST / AutoSA
  AutoSA: Polyhedral-Based Systolic Array Compiler
  ☆225Updated 2 years ago
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆282Updated 2 weeks ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆81Updated 6 years ago
• MPSLab-ASU / ccf
  CGRA Compilation Framework
  ☆88Updated 2 years ago
• Xtra-Computing / ThunderGP
  HLS-based Graph Processing Framework on FPGAs
  ☆149Updated 2 years ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆91Updated 6 months ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆66Updated 4 years ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆114Updated this week
• pnnl / OpenCGRA
  OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
  ☆160Updated 2 years ago
• harvard-acc / ALADDIN
  A pre-RTL, power-performance model for fixed-function accelerators
  ☆180Updated last year
• RC4ML / Shuhai
  Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…
  ☆117Updated 3 months ago
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆201Updated 5 years ago
• spcl / hls_tutorial_examples
  Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
  ☆201Updated 3 years ago
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆127Updated 2 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated last year
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆74Updated 3 weeks ago
• Xilinx / merlin-compiler
  ☆58Updated 2 years ago
• ucb-bar / gemmini-rocc-tests
  Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
  ☆60Updated 3 months ago
• StanfordAHA / aha
  ☆61Updated this week
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆48Updated 7 months ago
• Xilinx / logicnets
  Train and deploy LUT-based neural networks on FPGAs
  ☆99Updated last year
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆84Updated last year
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆54Updated 5 years ago
• zslwyuan / Light-HLS
  Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)
  ☆61Updated 3 years ago