cornell-zhang / rosettaLinks
Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
☆167Updated last year
Alternatives and similar repositories for rosetta
Users that are interested in rosetta are comparing it to the libraries listed below
Sorting:
- Benchmarks for Accelerator Design and Customized Architectures☆129Updated 5 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆124Updated 2 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆174Updated last month
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆136Updated 2 months ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆201Updated 3 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆77Updated 6 years ago
- An integrated CGRA design framework☆90Updated 5 months ago
- ☆87Updated last year
- AutoSA: Polyhedral-Based Systolic Array Compiler☆223Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated 11 months ago
- A DSL for Systolic Arrays☆81Updated 6 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- Train and deploy LUT-based neural networks on FPGAs☆98Updated last year
- CGRA Compilation Framework☆87Updated 2 years ago
- Next generation CGRA generator☆114Updated this week
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆114Updated 3 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 3 years ago
- HLS-based Graph Processing Framework on FPGAs☆149Updated 2 years ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆281Updated 4 months ago
- ☆72Updated 2 years ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆158Updated 2 years ago
- ☆60Updated this week
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆69Updated 6 years ago
- Library of approximate arithmetic circuits☆55Updated 3 years ago
- ☆30Updated 6 years ago
- A pre-RTL, power-performance model for fixed-function accelerators☆179Updated last year
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆60Updated 2 months ago
- Automatic generation of FPGA-based learning accelerators for the neural network family☆67Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago