cornell-zhang / rosettaLinks
Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)
☆169Updated 2 years ago
Alternatives and similar repositories for rosetta
Users that are interested in rosetta are comparing it to the libraries listed below
Sorting:
- Benchmarks for Accelerator Design and Customized Architectures☆135Updated 5 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆176Updated 4 months ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 2 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆149Updated this week
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆81Updated 6 years ago
- ☆87Updated last year
- An integrated CGRA design framework☆91Updated 9 months ago
- A DSL for Systolic Arrays☆83Updated 7 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆232Updated 3 years ago
- CGRA Compilation Framework☆89Updated 2 years ago
- HLS-based Graph Processing Framework on FPGAs☆150Updated 3 years ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆287Updated last month
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆204Updated 4 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆62Updated 3 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆70Updated 2 years ago
- Next generation CGRA generator☆118Updated last week
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆164Updated 2 years ago
- ☆60Updated 2 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆205Updated 5 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 3 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆117Updated 6 months ago
- SDAccel Development Environment Tutorials☆109Updated 5 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆61Updated 5 months ago
- Train and deploy LUT-based neural networks on FPGAs☆108Updated last year
- Fast and accurate DRAM power and energy estimation tool☆188Updated 2 months ago
- An Open-Source Tool for CGRA Accelerators☆80Updated 3 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆73Updated last week