cornell-zhang / rosetta

Related projects: ⓘ

• rapidstream-org / rapidstream-tapa
  RapidStream-TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.
  ☆149Updated this week
• UCLA-VAST / AutoSA
  AutoSA: Polyhedral-Based Systolic Array Compiler
  ☆192Updated last year
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆113Updated 4 years ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆102Updated this week
• UCLA-VAST / AutoBridge
  [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
  ☆117Updated last year
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆169Updated 4 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆56Updated 2 years ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆62Updated 5 years ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆173Updated 3 months ago
• lana555 / dynamatic
  ☆86Updated 6 months ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆62Updated last month
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆253Updated last week
• RC4ML / Shuhai
  Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…
  ☆92Updated last year
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆73Updated 5 years ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆82Updated 9 months ago
• pnnl / OpenCGRA
  OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
  ☆131Updated last year
• Xilinx / SDAccel-Tutorials
  SDAccel Development Environment Tutorials
  ☆106Updated 4 years ago
• Xtra-Computing / ThunderGP
  HLS-based Graph Processing Framework on FPGAs
  ☆135Updated last year
• harvard-acc / gem5-aladdin
  End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.
  ☆212Updated last year
• spcl / hls_tutorial_examples
  Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
  ☆188Updated 2 years ago
• MPSLab-ASU / ccf
  CGRA Compilation Framework
  ☆77Updated last year
• tukl-msd / DRAMPower
  Fast and accurate DRAM power and energy estimation tool
  ☆118Updated 2 weeks ago
• harvard-acc / smaug
  SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin
  ☆96Updated last year
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆162Updated 3 weeks ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆77Updated last month
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆106Updated 3 years ago
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆50Updated last month
• xupgit / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆70Updated 5 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆46Updated 3 years ago
• ehw-fit / evoapproxlib
  Library of approximate arithmetic circuits
  ☆46Updated 2 years ago