cornell-zhang / rosetta
Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
☆164Updated last year
Alternatives and similar repositories for rosetta:
Users that are interested in rosetta are comparing it to the libraries listed below
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆122Updated last week
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆165Updated this week
- Benchmarks for Accelerator Design and Customized Architectures☆121Updated 5 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆266Updated 5 months ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆188Updated 4 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- An integrated CGRA design framework☆87Updated 3 weeks ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆70Updated 5 years ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆199Updated 3 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆218Updated 2 years ago
- HLS-based Graph Processing Framework on FPGAs☆144Updated 2 years ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆147Updated 2 years ago
- A pre-RTL, power-performance model for fixed-function accelerators☆174Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆90Updated 6 months ago
- CGRA Compilation Framework☆83Updated last year
- Fast and accurate DRAM power and energy estimation tool☆154Updated this week
- Vitis HLS Library for FINN☆191Updated last week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆51Updated 5 years ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆231Updated 2 years ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆137Updated this week
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆106Updated last year
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆108Updated 2 years ago
- A Chisel RTL generator for network-on-chip interconnects☆193Updated last month
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆182Updated 4 years ago
- ☆91Updated last year
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆151Updated last year
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆319Updated 2 months ago
- A DSL for Systolic Arrays☆78Updated 6 years ago