cornell-zhang / rosettaLinks
Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
☆167Updated last year
Alternatives and similar repositories for rosetta
Users that are interested in rosetta are comparing it to the libraries listed below
Sorting:
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆174Updated last week
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆136Updated 2 months ago
- Benchmarks for Accelerator Design and Customized Architectures☆129Updated 5 years ago
- ☆87Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆77Updated 6 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆222Updated 2 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆198Updated 5 years ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆114Updated 2 months ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆279Updated 4 months ago
- A DSL for Systolic Arrays☆80Updated 6 years ago
- Next generation CGRA generator☆113Updated 3 weeks ago
- An integrated CGRA design framework☆90Updated 5 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated 10 months ago
- HLS-based Graph Processing Framework on FPGAs☆148Updated 2 years ago
- ☆60Updated this week
- Train and deploy LUT-based neural networks on FPGAs☆97Updated last year
- CGRA Compilation Framework☆86Updated 2 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆155Updated 2 years ago
- ☆92Updated last year
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆200Updated 3 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆83Updated last year
- Fast and accurate DRAM power and energy estimation tool☆173Updated last week
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆69Updated last year
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆60Updated 3 years ago
- ☆58Updated 2 years ago