Xilinx / finn-examplesLinks
Dataflow QNN inference accelerator examples on FPGAs
☆241Updated 4 months ago
Alternatives and similar repositories for finn-examples
Users that are interested in finn-examples are comparing it to the libraries listed below
Sorting:
- Vitis HLS Library for FINN☆213Updated last week
- DPU on PYNQ☆238Updated 5 months ago
- Convolutional Neural Network Using High Level Synthesis☆90Updated 5 years ago
- PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform☆74Updated 5 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆373Updated 11 months ago
- AMD University Program HLS tutorial☆124Updated last year
- Tutorial notebooks for hls4ml☆401Updated last week
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 4 years ago
- ☆104Updated 2 years ago
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆282Updated 6 years ago
- This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.☆107Updated 3 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆241Updated 2 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆51Updated 5 years ago
- Research and Materials on Hardware implementation of Transformer Model☆296Updated 10 months ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆223Updated last year
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆107Updated 7 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆41Updated last year
- FPGA based Vision Transformer accelerator (Harvard CS205)☆144Updated 11 months ago
- IC implementation of Systolic Array for TPU☆324Updated last year
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆168Updated 2 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆162Updated this week
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆177Updated last year
- Verilog implementation of Softmax function☆77Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆178Updated 6 years ago
- ☆250Updated 5 years ago
- Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design con…☆113Updated 7 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆119Updated 11 months ago
- PYNQ, Neural network Language model, Overlay☆112Updated 6 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆196Updated 8 years ago
- An FPGA Accelerator for Transformer Inference☆92Updated 3 years ago