Xilinx / finn-examples
Dataflow QNN inference accelerator examples on FPGAs
☆207Updated 2 months ago
Alternatives and similar repositories for finn-examples:
Users that are interested in finn-examples are comparing it to the libraries listed below
- Vitis HLS Library for FINN☆191Updated last week
- DPU on PYNQ☆211Updated last year
- Convolutional Neural Network Using High Level Synthesis☆86Updated 4 years ago
- Tutorial notebooks for hls4ml☆325Updated this week
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆331Updated 2 months ago
- IC implementation of Systolic Array for TPU☆204Updated 5 months ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆144Updated 9 months ago
- ☆247Updated 4 years ago
- PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform☆69Updated 4 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆185Updated last year
- This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.☆101Updated 2 years ago
- ☆86Updated last year
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆131Updated this week
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆137Updated last year
- Research and Materials on Hardware implementation of Transformer Model☆246Updated 3 weeks ago
- Dataflow compiler for QNN inference on FPGAs☆795Updated this week
- Board files to build Ultra 96 PYNQ image☆154Updated 3 months ago
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆265Updated 5 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆157Updated 11 months ago
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆209Updated 5 years ago
- ☆103Updated 4 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆57Updated 3 years ago
- PYNQ, Neural network Language model, Overlay☆106Updated 5 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆104Updated 6 years ago
- Computer Vision Overlays on Pynq☆178Updated 5 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆177Updated 7 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆146Updated 5 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆317Updated 2 months ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆199Updated 3 years ago
- ☆190Updated 2 months ago