Alternatives and similar repositories for PYNQ_tutorials

Users that are interested in PYNQ_tutorials are comparing it to the libraries listed below

• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆84Updated last year
• Xilinx / xup_high_level_synthesis_design_flow
  AMD University Program HLS tutorial
  ☆95Updated 7 months ago
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆221Updated last year
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆72Updated 11 months ago
• manoharvhr / PYNQ-Torch
  PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform
  ☆71Updated 4 years ago
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆87Updated 4 years ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆198Updated this week
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆152Updated 11 months ago
• xupgit / Advanced-Embedded-System-Design-Flow-on-Zynq
  ☆52Updated 6 years ago
• Xilinx / Vivado-Design-Tutorials
  ☆210Updated last month
• Xilinx / PYNQ-HelloWorld
  This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.
  ☆104Updated 2 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆65Updated 6 years ago
• JinChen-tw / pynqz2_dpu140
  This TRD is implement DPU v1.4.0 on PYNQ-Z2 board
  ☆45Updated 4 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆75Updated last year
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆160Updated 5 years ago
• andre1araujo / YOLO-on-PYNQ-Z2
  This repository contains all the necessary material to implement a YOLOv3 object detection algorithm on the PYNQ-Z2 FPGA. There is a step…
  ☆58Updated 2 months ago
• Xilinx / Kria-PYNQ
  PYNQ support and examples for Kria SOMs
  ☆109Updated 9 months ago
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆155Updated 5 months ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆105Updated 7 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆85Updated 6 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆64Updated 9 months ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆103Updated 4 years ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆205Updated 2 years ago
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆31Updated 2 years ago
• sumanth-kalluri / cnn_hardware_acclerator_for_fpga
  This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…
  ☆180Updated last year
• drichmond / RISC-V-On-PYNQ
  RISC-V Integration for PYNQ
  ☆173Updated 5 years ago
• maomran / softmax
  Verilog implementation of Softmax function
  ☆66Updated 2 years ago
• canteen-man / CNN_FPGA_ZYNQ_PYNQ
  hls code zynq 7020 pynq z2 CNN
  ☆85Updated 6 years ago
• embedeep / FREE-TPU-V3plus-for-FPGA
  FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
  ☆146Updated last year
• AniketBadhan / Convolutional-Neural-Network
  Implementation of CNN using Verilog
  ☆217Updated 7 years ago