XUANTIE-RV / opene906Links
OpenXuantie - OpenE906 Core
☆142Updated last year
Alternatives and similar repositories for opene906
Users that are interested in opene906 are comparing it to the libraries listed below
Sorting:
- OpenXuantie - OpenE902 Core☆159Updated last year
- OpenSource HummingBird RISC-V Software Development Kit☆165Updated last year
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆217Updated 5 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆127Updated 6 years ago
- ☆96Updated 2 months ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆124Updated 3 years ago
- Basic RISC-V Test SoC☆153Updated 6 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆112Updated 3 years ago
- The Ultra-Low Power RISC Core☆15Updated 5 years ago
- OpenXuantie - OpenC906 Core☆371Updated last year
- Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/☆112Updated 4 years ago
- AMBA bus generator including AXI, AHB, and APB☆107Updated 4 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆141Updated last year
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆75Updated 4 years ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆275Updated 5 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆130Updated 5 years ago
- AHB3-Lite Interconnect☆94Updated last year
- ☆44Updated 3 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆277Updated last week
- 8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.☆193Updated 6 years ago
- SystemC/TLM-2.0 Co-simulation framework☆256Updated 5 months ago
- AXI4 and AXI4-Lite interface definitions☆96Updated 5 years ago
- Verilog implementation of a RISC-V core☆125Updated 7 years ago
- AXI Interface Nand Flash Controller (Sync mode)☆96Updated last year
- Verilog UART☆183Updated 12 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- ☆144Updated 5 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- 国产VU13P加速卡资料☆79Updated 7 months ago
- ☆245Updated 2 years ago