XUANTIE-RV / opensbiLinks
☆17Updated 4 months ago
Alternatives and similar repositories for opensbi
Users that are interested in opensbi are comparing it to the libraries listed below
Sorting:
- riscv64 d1-nezha baremeta(Allwinner D1 riscv chip)☆87Updated 3 years ago
- Nuclei RISC-V Software Development Kit☆154Updated 2 weeks ago
- GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……☆106Updated 8 months ago
- Qemu for Xuantie RISC-V CPU, a generic machine emulator and virtualizer.☆49Updated 5 months ago
- Linux kernel source tree☆45Updated 10 months ago
- DEPRECATED: Please update to risc-none-elf-gcc-xpack☆125Updated 3 years ago
- 8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.☆196Updated 6 years ago
- RISC-V Scratchpad☆73Updated 3 years ago
- RISC-V Profiles and Platform Specification☆116Updated 2 years ago
- OpenXuantie - OpenE906 Core☆151Updated last year
- OpenXuantie - OpenC906 Core☆380Updated last year
- 8051 core☆109Updated 11 years ago
- Implemetation of pipelined ARM7TDMI processor in Verilog☆91Updated 7 years ago
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆89Updated 5 years ago
- A RISC-V bare metal example☆54Updated 3 years ago
- The GNU MCU Eclipse RISC-V Embedded GCC☆79Updated 6 years ago
- open-source SDKs for the SCR1 core☆76Updated last year
- Spen's Official OpenOCD Mirror☆51Updated 9 months ago
- TCP/IP controlled VPI JTAG Interface.☆69Updated 11 months ago
- Testing the speed of CPU and more on generations of hardware.☆51Updated 4 months ago
- PLIC Specification☆150Updated 4 months ago
- Simple machine mode program to probe RISC-V control and status registers☆127Updated 2 years ago
- Official Intel SOCFPGA U-Boot repository. Note: (1) A "RC" labeled branch is for internal active development use and customer early acces…☆115Updated last month
- OpenXuantie - OpenE902 Core☆165Updated last year
- RISC-V port of newlib☆102Updated 3 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆72Updated last year
- Yocto project for Xuantie RISC-V CPU☆40Updated 4 months ago
- 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.☆27Updated 2 years ago
- Verilog implementation of a RISC-V core☆133Updated 7 years ago
- OpenEmbedded/Yocto layer for RISC-V Architecture☆417Updated 2 weeks ago