Alternatives and similar repositories for dma_ahb

Users that are interested in dma_ahb are comparing it to the libraries listed below

• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆120Updated 11 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆75Updated 11 years ago
• freecores / apbi2c
  APB to I2C
  ☆43Updated 11 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆79Updated last year
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆36Updated 10 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆41Updated 3 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆94Updated 4 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆106Updated 4 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆96Updated 6 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆52Updated 4 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆61Updated 3 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆39Updated 3 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆103Updated 5 years ago
• ptracton / AXI_BFM
  AXI4 BFM in Verilog
  ☆33Updated 8 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆58Updated last year
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆64Updated last year
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆66Updated last year
• ForrestBlue / cortexm0ds
  ☆68Updated 9 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆90Updated 3 years ago
• nelsoncsc / ISP_UVM
  A Framework for Design and Verification of Image Processing Applications using UVM
  ☆106Updated 7 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆49Updated 5 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆92Updated last year
• Verdvana / AXI_SRAM
  支持AXI总线协议的8k×8 SP SRAM
  ☆25Updated 5 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 6 years ago
• Buddhimah / System-Bus-Design-Verilog
  This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification
  ☆32Updated 5 years ago
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆64Updated last year
• brown9804 / PCIe-Physical-Layer
  Implementation of the PCIe physical layer
  ☆48Updated 2 months ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆71Updated 4 years ago
• freecores / robust_axi2ahb
  Generic AXI to AHB bridge
  ☆17Updated 11 years ago
• IA-C-Lab-Fudan / Chisel-FFT-generator
  FFT generator using Chisel
  ☆62Updated 3 years ago