freecores / dma_ahb

Related projects ⓘ

Alternatives and complementary repositories for dma_ahb

• Lianghao-Yuan / AHB_Bus_Matrix
  ☆33Updated 9 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆31Updated 2 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆97Updated 10 years ago
• freecores / apbi2c
  APB to I2C
  ☆40Updated 10 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆41Updated 6 months ago
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆32Updated 7 years ago
• ptracton / AXI_BFM
  AXI4 BFM in Verilog
  ☆32Updated 7 years ago
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆54Updated last year
• wanderingnail / AXI_DMA
  ☆15Updated last year
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆44Updated 5 months ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆45Updated 3 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆83Updated 4 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆66Updated 10 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆53Updated 2 months ago
• Buddhimah / System-Bus-Design-Verilog
  This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification
  ☆31Updated 4 years ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆50Updated 7 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆29Updated 6 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆90Updated 4 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆55Updated 9 months ago
• pulp-platform / axi_spi_master
  ☆20Updated 5 years ago
• red435 / verilog_APB_SPI_interface
  SPI interface connect to APB BUS with Verilog HDL
  ☆25Updated 3 years ago
• kdurant / axi-ddr3
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆35Updated 7 years ago
• jessepalomera / 10G_EthernetMAC_SystemVerilog_OOP
  Final Project for my course in Advanced Verification with SystemVerilog OOP
  ☆20Updated 2 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆28Updated 2 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆49Updated 4 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆37Updated 4 years ago
• freecores / robust_axi2ahb
  Generic AXI to AHB bridge
  ☆15Updated 10 years ago
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆41Updated 7 months ago
• kuladeepsaireddy / OpenNoc
  ☆26Updated 5 years ago