Alternatives and similar repositories for epwave:

Users that are interested in epwave are comparing it to the libraries listed below

• go2uvm / go2uvm
  Main repo for Go2UVM source code, examples and apps
  ☆20Updated last year
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆16Updated 5 years ago
• ben-marshall / verilog-doc
  A basic documentation generator for Verilog, similar to Doxygen.
  ☆11Updated 8 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• freecores / wb_builder
  WISHBONE Builder
  ☆14Updated 8 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 4 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆17Updated last year
• open-design / riscv-soc-cores
  ☆37Updated 3 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆35Updated 8 months ago
• Paebbels / PicoBlaze-Library
  The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…
  ☆34Updated 4 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• pulp-platform / hyperbus
  ☆21Updated last month
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆35Updated last month
• ultraembedded / cortex_m0_wrapper
  Cortex-M0 DesignStart Wrapper
  ☆17Updated 5 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆55Updated last year
• drom / logidrom
  Digital Circuit rendering engine
  ☆36Updated last year
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated last year
• IObundle / iob-lib
  Verilog Modules and Python Scripts for Creating IP Core Build Directories
  ☆29Updated last year
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆38Updated 7 months ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆24Updated 7 months ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆39Updated 4 years ago
• umarcor / hwstudio
  GUI editor for hardware description designs
  ☆27Updated last year
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆24Updated last year
• freecores / 1000base-x
  1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)
  ☆18Updated 10 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 4 months ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆37Updated 5 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆76Updated 2 years ago
• RISCV-on-Microsemi-FPGA / SoftConsole
  Eclipse based IDE for RISC-V bare metal software development.
  ☆18Updated 5 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated last week