whutddk / RiftCoreLinks
RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
☆42Updated 2 years ago
Alternatives and similar repositories for RiftCore
Users that are interested in RiftCore are comparing it to the libraries listed below
Sorting:
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆62Updated 5 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆65Updated 2 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆86Updated last week
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆40Updated last year
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆45Updated 3 years ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 4 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆69Updated 11 months ago
- The multi-core cluster of a PULP system.☆105Updated this week
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆49Updated 8 months ago
- For contributions of Chisel IP to the chisel community.☆64Updated 8 months ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆169Updated 3 weeks ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 6 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆41Updated 2 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆112Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆111Updated this week
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated 11 months ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆58Updated last week
- Platform Level Interrupt Controller☆41Updated last year
- Vector processor for RISC-V vector ISA☆121Updated 4 years ago
- Chisel RISC-V Vector 1.0 Implementation☆103Updated 2 months ago
- RISC-V Verification Interface☆97Updated last month
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆110Updated last year
- Simple runtime for Pulp platforms☆48Updated this week
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆41Updated 8 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆36Updated last year
- ☆61Updated 4 years ago