whutddk / RiftCoreLinks
RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
☆44Updated 3 years ago
Alternatives and similar repositories for RiftCore
Users that are interested in RiftCore are comparing it to the libraries listed below
Sorting:
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Updated last year
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- The multi-core cluster of a PULP system.☆109Updated 2 weeks ago
- pulp_soc is the core building component of PULP based SoCs☆81Updated 8 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 weeks ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆186Updated last month
- For contributions of Chisel IP to the chisel community.☆67Updated last year
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆92Updated last week
- Generic Register Interface (contains various adapters)☆133Updated last month
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆70Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆123Updated 4 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated last year
- ☆87Updated last week
- Vector processor for RISC-V vector ISA☆130Updated 5 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆123Updated last week
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated 10 months ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- Platform Level Interrupt Controller☆43Updated last year
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆71Updated last year
- 64-bit multicore Linux-capable RISC-V processor☆99Updated 6 months ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- RISC-V Verification Interface☆119Updated this week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆112Updated 2 years ago
- Simple runtime for Pulp platforms☆49Updated last week
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week