CustomizableComputingLab / Nexysvideo_wujian100
☆14Updated 3 years ago
Alternatives and similar repositories for Nexysvideo_wujian100:
Users that are interested in Nexysvideo_wujian100 are comparing it to the libraries listed below
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆33Updated 2 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆36Updated 7 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆18Updated 7 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals,this SoC run a CNN. The…☆10Updated last year
- ☆25Updated 4 years ago
- ☆9Updated 4 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆47Updated 3 years ago
- ☆26Updated 5 years ago
- AHB DMA 32 / 64 bits☆52Updated 10 years ago
- ☆19Updated 2 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆18Updated 3 months ago
- Interface Protocol in Verilog☆48Updated 5 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆35Updated 2 years ago
- ☆37Updated 2 years ago
- ☆36Updated 6 years ago
- System on Chip verified with UVM/OSVVM/FV☆23Updated 3 weeks ago
- a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.☆11Updated 5 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆57Updated last year
- A verilog implementation for Network-on-Chip☆71Updated 6 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆13Updated 3 years ago
- ☆50Updated 3 years ago
- ☆23Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆61Updated 4 years ago
- General Purpose AXI Direct Memory Access☆48Updated 8 months ago
- ☆35Updated 9 years ago
- ☆20Updated 5 years ago