CustomizableComputingLab / Nexysvideo_wujian100Links
☆15Updated 3 years ago
Alternatives and similar repositories for Nexysvideo_wujian100
Users that are interested in Nexysvideo_wujian100 are comparing it to the libraries listed below
Sorting:
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- ☆29Updated 5 years ago
- ☆34Updated 6 years ago
- ☆21Updated 3 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆65Updated last year
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆77Updated 2 years ago
- ☆60Updated 3 years ago
- A verilog implementation for Network-on-Chip☆76Updated 7 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 8 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- ☆11Updated 4 years ago
- EE 272B - VLSI Design Project☆13Updated 4 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆31Updated 4 years ago
- SDRAM controller with AXI4 interface☆96Updated 6 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆79Updated 7 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆35Updated 4 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- ☆66Updated 3 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Updated 5 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals,this SoC run a CNN. The…☆13Updated 2 years ago
- ☆53Updated 6 years ago
- Simple single-port AXI memory interface☆45Updated last year
- upgrade to e203 (a risc-v core)☆44Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated 3 weeks ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆66Updated last year