Alternatives and similar repositories for tage:

Users that are interested in tage are comparing it to the libraries listed below

• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆41Updated 3 years ago
• OpenXiangShan / GEM5
  ☆74Updated this week
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆58Updated last year
• CMU-SAFARI / Hermes
  A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…
  ☆72Updated 5 months ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆70Updated 5 years ago
• eric-rotenberg / CVP
  Championship Value Prediction (CVP) simulator.
  ☆15Updated 4 years ago
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆17Updated last month
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆62Updated 8 months ago
• PolyArch / gem-forge-framework
  ☆24Updated last year
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆54Updated last year
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆47Updated last year
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆48Updated 7 years ago
• agusnt / Berti-Artifact
  An artifact for Berti: an Accurate and Timely Local-Delta Data Prefetcher
  ☆28Updated 2 years ago
• TeCSAR-UNCC / gem5-SALAM
  ☆91Updated last year
• lizhirui / DreamCoreV2
  ☆21Updated last year
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• sequencer / arithmetic
  ☆32Updated 2 weeks ago
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆31Updated last year
• RoyanTuscano / -TAGE-based-Predictor-Verilog-Code
  Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud
  ☆17Updated 6 years ago
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆58Updated last month
• cdsc-github / parade-ara-simulator
  PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration
  ☆47Updated 2 years ago
• meton-robean / Vector_MulAdd_Accelerator
  vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
  ☆51Updated 4 years ago
• comparch-security / spike-cache
  Spike with a coherence supported cache model
  ☆13Updated 7 months ago
• ppeetteerrs / gem5-RISC-V-FS-Linux
  Repository containing the guide and code for booting RISC-V full system linux using gem5.
  ☆48Updated 3 years ago
• m-asiatici / MSHR-rich
  A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…
  ☆18Updated 4 years ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆86Updated 3 months ago
• cry-daniel / Computer-Architecture-Learning
  ☆58Updated 2 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆33Updated 4 years ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆74Updated 9 years ago