Alternatives and similar repositories for tage

Users that are interested in tage are comparing it to the libraries listed below

• OpenXiangShan / GEM5
  ☆113Updated last week
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 3 years ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆123Updated last year
• HewlettPackard / mcpat
  An integrated power, area, and timing modeling framework for multicore and manycore architectures
  ☆205Updated 5 years ago
• tukl-msd / DRAMPower
  Fast and accurate DRAM power and energy estimation tool
  ☆186Updated last month
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆69Updated last year
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• CMU-SAFARI / Hermes
  A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…
  ☆76Updated 2 months ago
• snipersim / snipersim
  The Sniper Multi-Core Simulator
  ☆162Updated last month
• cry-daniel / Computer-Architecture-Learning
  ☆65Updated 2 years ago
• eric-rotenberg / CVP
  Championship Value Prediction (CVP) simulator.
  ☆17Updated 4 years ago
• gem5 / gem5-resources
  The official repository for the gem5 resources sources.
  ☆73Updated 3 weeks ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆72Updated last year
• TeCSAR-UNCC / gem5-SALAM
  ☆106Updated last year
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆59Updated 3 years ago
• ppeetteerrs / gem5-RISC-V-FS-Linux
  Repository containing the guide and code for booting RISC-V full system linux using gem5.
  ☆56Updated 4 years ago
• arm-university / arm-gem5-rsk
  Official repository of the Arm Research Starter Kit on System Modeling using gem5
  ☆117Updated 5 months ago
• ramisheikh / cbp2025
  Championship Branch Prediction 2025
  ☆62Updated 6 months ago
• UT-LCA / Scalability-Phase-Simpoint-of-SPEC-CPU2017
  ☆34Updated 5 years ago
• tukl-msd / gem5.TnT
  gem5 Tips & Tricks
  ☆70Updated 5 years ago
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆33Updated 2 years ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆95Updated 2 weeks ago
• esl-epfl / gem5-X
  The gem5-X open source framework (based on the gem5 simulator)
  ☆42Updated 2 years ago
• powerjg / learning_gem5
  Learning gem5 is a work-in-progress book to help gem5 users get started using gem5.
  ☆191Updated 2 years ago
• gem5bootcamp / gem5-bootcamp-env
  The gem5 Bootcamp 2022 environment. Archived.
  ☆35Updated last year
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆19Updated 6 months ago
• agusnt / Berti-Artifact
  An artifact for Berti: an Accurate and Timely Local-Delta Data Prefetcher
  ☆35Updated 3 years ago
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆191Updated last week
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆155Updated 9 months ago