Alternatives and similar repositories for ahb_master

Users that are interested in ahb_master are comparing it to the libraries listed below

• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 11 years ago
• open-dv / dma_axi
  ☆16Updated 6 years ago
• pulp-platform / redundancy_cells
  SystemVerilog IPs and Modules for architectural redundancy designs.
  ☆14Updated this week
• eanchlia / NN_Network_On_Chip
  Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…
  ☆12Updated 6 years ago
• GuiZhaoCodeSource / Func_Verif_MMU_Code_Source
  Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache
  ☆13Updated 9 years ago
• freecores / an-fpga-implementation-of-low-latency-noc-based-mpsoc
  NoC based MPSoC
  ☆11Updated 11 years ago
• ZipCPU / axidmacheck
  AXI DMA Check: A utility to measure DMA speeds in simulation
  ☆15Updated 5 months ago
• muneebullashariff / pulpino_soc_uvm_testbench
  UVM testbench for verifying the Pulpino SoC
  ☆13Updated 5 years ago
• vfinotti / ahb3lite_dma
  DMA core compatible with AHB3-Lite
  ☆10Updated 6 years ago
• gjlies / configgpgpu
  A configurable general purpose graphics processing unit for
  ☆11Updated 6 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• gauravtewari / python-to-verilog
  Generate a Verilog Source file and testbench file for a given Moore FSM
  ☆17Updated 12 years ago
• pulp-platform / axi_node
  AXI X-Bar
  ☆19Updated 5 years ago
• efabless / raptor_soc_template
  Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
  ☆21Updated 5 years ago
• pulp-platform / hier-icache
  ☆12Updated 4 months ago
• ShonTaware / LowPower
  Various low power labs using sky130
  ☆12Updated 3 years ago
• PacoReinaCampo / MPSoC-DMA
  Direct Access Memory for MPSoC
  ☆13Updated last month
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆17Updated 5 years ago
• freecores / divider
  Hardware Division Units
  ☆10Updated 11 years ago
• briandong / regModel
  This script builds the UVM register model, based on pre-defined address map in markdown (mk) style
  ☆12Updated 7 years ago
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆11Updated 4 years ago
• fengyulin1996 / Verilog-DSP
  FIR，FFT based on Verilog
  ☆13Updated 7 years ago
• rakeshgehalot / Ethernet_switch_verification
  Verification of Ethernet Switch System Verilog
  ☆11Updated 8 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆30Updated 8 years ago
• Elrori / OV_camera_on_FPGA
  OV7670 (Verilog HDL)Drive for FPGA
  ☆17Updated 6 years ago
• pulp-platform / axi_llc
  ☆30Updated last week
• emmanouil-komninos / jtag_vip_uvm
  ☆12Updated 9 years ago
• freecores / wdsp
  DSP WishBone Compatible Cores
  ☆14Updated 11 years ago
• baochuquan / RISCV-MMU
  ☆14Updated 7 years ago
• CospanDesign / verilog_ppfifo_demo
  Simple demo showing how to use the ping pong FIFO
  ☆14Updated 9 years ago