freecores / ahb_master
Generic AHB master stub
☆11Updated 10 years ago
Alternatives and similar repositories for ahb_master
Users that are interested in ahb_master are comparing it to the libraries listed below
Sorting:
- Various low power labs using sky130☆12Updated 3 years ago
- ☆14Updated 5 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Updated 9 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆11Updated 4 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆19Updated 5 years ago
- Generic AXI master stub☆19Updated 10 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆16Updated 5 years ago
- FIR,FFT based on Verilog☆13Updated 7 years ago
- ☆12Updated 2 months ago
- DSP WishBone Compatible Cores☆13Updated 10 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Updated 3 months ago
- ☆16Updated 6 years ago
- Simple demo showing how to use the ping pong FIFO☆14Updated 9 years ago
- A configurable general purpose graphics processing unit for☆11Updated 5 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Updated 6 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- NoC based MPSoC☆10Updated 10 years ago
- A Verilog AMBA AHB Multilayer interconnect generator☆12Updated 7 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆14Updated last week
- ☆12Updated 9 years ago
- Direct Access Memory for MPSoC☆12Updated this week
- AXI X-Bar☆19Updated 5 years ago
- double_fpu_verilog☆15Updated 10 years ago
- ☆14Updated 7 years ago
- WISHBONE Interconnect☆11Updated 7 years ago
- Generic AXI to APB bridge☆12Updated 10 years ago