aaronshappell / tage-predictor
SystemVerilog implemention of the TAGE branch predictor
☆11Updated 3 years ago
Alternatives and similar repositories for tage-predictor:
Users that are interested in tage-predictor are comparing it to the libraries listed below
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆14Updated 2 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆18Updated this week
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- ☆22Updated last year
- Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud☆19Updated 6 years ago
- ☆19Updated last week
- Xiangshan deterministic workloads generator☆17Updated 3 weeks ago
- Advanced Architecture Labs with CVA6☆55Updated last year
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆31Updated last year
- data preprocessing scripts for gem5 output☆17Updated 2 months ago
- "aura" my super-scalar O3 cpu core☆24Updated 10 months ago
- RISC-V Matrix Specification☆19Updated 3 months ago
- ☆40Updated 2 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆24Updated this week
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆51Updated 3 years ago
- 给NEMU移植Linux Kernel!☆14Updated this week
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆15Updated 5 months ago
- ☆17Updated 3 years ago
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆12Updated 3 months ago
- 关于移植模型至gemmini的文档☆23Updated 2 years ago
- Chisel RISC-V Vector 1.0 Implementation☆87Updated last month
- ☆32Updated this week
- ☆12Updated 2 months ago
- Running ahead of memory latency - Part II project☆10Updated 2 years ago
- Unit tests generator for RVV 1.0☆79Updated this week
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆16Updated 3 weeks ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆19Updated 11 months ago
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆26Updated 5 years ago
- ☆19Updated 3 years ago
- Lab assignments for the Agile Hardware Design course☆14Updated 11 months ago