aaronshappell / tage-predictorLinks
SystemVerilog implemention of the TAGE branch predictor
☆13Updated 4 years ago
Alternatives and similar repositories for tage-predictor
Users that are interested in tage-predictor are comparing it to the libraries listed below
Sorting:
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆29Updated this week
- Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud☆21Updated 7 years ago
- gem5 FS模式实验手册☆44Updated 2 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆59Updated 3 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated this week
- ☆22Updated 2 years ago
- "aura" my super-scalar O3 cpu core☆24Updated last year
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆15Updated 3 years ago
- CQU Dual Issue Machine☆38Updated last year
- ☆32Updated 4 months ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆43Updated 5 months ago
- ☆11Updated last year
- A docker image for One Student One Chip's debug exam☆11Updated 2 years ago
- Xiangshan deterministic workloads generator☆22Updated 6 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆30Updated 2 weeks ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆53Updated 3 years ago
- A Heterogeneous GPU Platform for Chipyard SoC☆39Updated this week
- RISC-V Matrix Specification☆23Updated 11 months ago
- Implementing the Precise Runahead (HPCA'20) in gem5☆13Updated 2 years ago
- Advanced Architecture Labs with CVA6☆71Updated last year
- ☆113Updated last week
- GPGPU-Sim 中文注释版代码,包含 GPGPU-Sim 模拟器的最新版代码,经过中文注释,以帮助中文用户更好地理解和使用该模拟器。☆27Updated 11 months ago
- Pick your favorite language to verify your chip.☆73Updated 2 weeks ago
- A Study of the SiFive Inclusive L2 Cache☆69Updated last year
- data preprocessing scripts for gem5 output☆19Updated 6 months ago
- ☆65Updated 2 years ago
- ☆50Updated 10 months ago
- Chisel RISC-V Vector 1.0 Implementation☆121Updated last month
- ☆17Updated 3 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆49Updated last year