aaronshappell / tage-predictorLinks
SystemVerilog implemention of the TAGE branch predictor
☆12Updated 4 years ago
Alternatives and similar repositories for tage-predictor
Users that are interested in tage-predictor are comparing it to the libraries listed below
Sorting:
- Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud☆20Updated 7 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆19Updated 2 weeks ago
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆14Updated 2 years ago
- "aura" my super-scalar O3 cpu core☆24Updated last year
- ☆21Updated 2 months ago
- Xiangshan deterministic workloads generator☆19Updated 3 weeks ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆55Updated 3 years ago
- ☆22Updated 2 years ago
- ☆33Updated 2 months ago
- GPGPU-Sim 中文注释版代码,包含 GPGPU-Sim 模拟器的最新版代码,经过中文注释,以帮助中文用户更好地理解和使用该模拟器。☆16Updated 5 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆27Updated 2 weeks ago
- 给NEMU移植Linux Kernel!☆18Updated this week
- An almost empty chisel project as a starting point for hardware design☆31Updated 4 months ago
- ☆17Updated 3 years ago
- data preprocessing scripts for gem5 output☆18Updated last week
- ☆18Updated 2 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- gem5 FS模式实验手册☆38Updated 2 years ago
- Running ahead of memory latency - Part II project☆10Updated 2 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆40Updated last year
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆48Updated last year
- The official NaplesPU hardware code repository☆16Updated 5 years ago
- ☆41Updated 4 months ago
- Advanced Architecture Labs with CVA6☆61Updated last year
- Spike with a coherence supported cache model☆13Updated 10 months ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated last month
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆17Updated last month
- Original test vector of RISC-V Vector Extension☆11Updated 4 years ago
- Implementing the Precise Runahead (HPCA'20) in gem5☆11Updated last year