Alternatives and similar repositories for yarvi

Users that are interested in yarvi are comparing it to the libraries listed below

• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆81Updated 5 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆85Updated 4 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆74Updated 6 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆144Updated last month
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆121Updated 6 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆109Updated last month
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆93Updated this week
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆41Updated last year
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆101Updated 6 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆181Updated 6 months ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆100Updated 6 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 5 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆105Updated 3 years ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆101Updated 3 years ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆49Updated 8 months ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆128Updated 5 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 3 months ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆122Updated 4 years ago
• leros-dev / leros
  A Tiny Processor Core
  ☆110Updated last month
• schoeberl / wildcat
  An implementation of RISC-V
  ☆34Updated this week
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆59Updated last month
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆93Updated 4 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆66Updated 5 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆86Updated last year
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆88Updated last year
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆83Updated 4 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆115Updated last year