Yet Another RISC-V Implementation
☆101Sep 21, 2024Updated 2 years ago
Alternatives and similar repositories for yarvi
Users that are interested in yarvi are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Feb 24, 2023Updated 3 years ago
- An implementation of RISC-V☆55Jul 14, 2026Updated 3 months ago
- YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…☆48Dec 4, 2024Updated last year
- Fluid dynamics for Lovebyte 2022 in 512 bytes☆10Feb 12, 2022Updated 4 years ago
- A 32-bit RISC-V processor for mriscv project☆63Jul 17, 2017Updated 9 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Arduino library for Microblaze and Cortex A9, integrated with Vivado/SDK☆11Dec 2, 2014Updated 11 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55May 30, 2017Updated 9 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Aug 28, 2019Updated 7 years ago
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆386Jul 12, 2017Updated 9 years ago
- An open-source microcontroller system based on RISC-V☆1,073Feb 6, 2024Updated 2 years ago
- RISC-V CPU Core☆454Jun 24, 2025Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆139Jul 11, 2025Updated last year
- A RISC-V processor☆14Dec 11, 2018Updated 7 years ago
- Generated html for the lowRISC site. PRs should go to the source repo https://github.com/lowrisc/lowrisc-site☆13Jun 25, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Clarvi simple RISC-V processor for teaching☆58Aug 25, 2017Updated 9 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,394Sep 7, 2026Updated last month
- RISC-V RV32E core designed for minimal area☆27Nov 17, 2024Updated last year
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆426Oct 22, 2026Updated last week
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆26Nov 21, 2020Updated 5 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆70May 30, 2022Updated 4 years ago
- WISHBONE Builder☆15Sep 10, 2016Updated 10 years ago
- Featherweight RISC-V implementation☆53Jan 17, 2022Updated 4 years ago
- Is a collection of NULL Convention Logic (NCL) circuits and libraries written in Verilog to provide the experience of logically determine…☆16Jun 15, 2016Updated 10 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, op…☆112Sep 17, 2022Updated 4 years ago
- A small 32-bit implementation of the RISC-V architecture☆34Aug 21, 2026Updated 2 months ago
- RISC-V BSV Specification☆24Apr 28, 2026Updated 6 months ago
- Mini RISC-V SOC☆13Nov 13, 2015Updated 10 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,300Oct 13, 2026Updated 2 weeks ago
- educational microarchitectures for risc-v isa☆758Sep 1, 2025Updated last year
- ☆18Nov 4, 2024Updated last year
- Yosys plugin for synthesis of Bluespec code☆17Sep 8, 2021Updated 5 years ago
- ☆32Sep 3, 2025Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A time-predictable processor for mixed-criticality systems☆64Nov 7, 2024Updated last year
- VeeR EH1 core☆972Jul 16, 2026Updated 3 months ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆166Jan 25, 2024Updated 2 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆23Oct 2, 2026Updated 3 weeks ago
- RISC-V processor☆32May 26, 2022Updated 4 years ago
- Acorn Atom in minimal configuration for iCE40 HX8K board and ICOboard☆10Apr 30, 2023Updated 3 years ago
- A design for TinyTapeout☆18Sep 23, 2022Updated 4 years ago