SDIO Device Verilog Core
☆25Jul 25, 2018Updated 8 years ago
Alternatives and similar repositories for nysa-sdio-device
Users that are interested in nysa-sdio-device are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆19Jul 25, 2018Updated 8 years ago
- Communication channel from FPGA (Alterra EP4CE10) and Linux (Lichee PI Allwinner V3S)☆30Apr 1, 2020Updated 6 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆37May 12, 2020Updated 6 years ago
- ☆92May 4, 2017Updated 9 years ago
- 基于USB2.0 的数据采集卡☆21Feb 20, 2019Updated 7 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆13Apr 29, 2015Updated 11 years ago
- Verification of Ethernet Switch System Verilog☆12Oct 21, 2016Updated 10 years ago
- An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。☆351Sep 14, 2023Updated 3 years ago
- A simple PDM microphone interface on FPGA☆15Jan 16, 2022Updated 4 years ago
- Verilog Repository for GIT☆37May 4, 2021Updated 5 years ago
- AXI PSRAM Controller IP for use with Digilent Nexys 4☆11Jun 19, 2026Updated 4 months ago
- USB 1.1 PHY☆12Jul 17, 2014Updated 12 years ago
- Imitate SDcard using FPGAs. 使用FPGA模拟伪装SD卡。☆140Sep 14, 2023Updated 3 years ago
- ECP5 FPGA DEV BOARD☆10Apr 19, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- DMA core compatible with AHB3-Lite☆13Mar 30, 2019Updated 7 years ago
- ProfiBus-DP to TCP/IP Ethernet☆26Mar 21, 2017Updated 9 years ago
- AMBA bus generator including AXI, AHB, and APB☆123Jul 29, 2021Updated 5 years ago
- Simply Cyclone IV EP4CE10 Developer board (KiCAD edition)☆10Nov 25, 2018Updated 7 years ago
- USB -> AXI Debug Bridge☆47Jun 5, 2021Updated 5 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆75Nov 22, 2019Updated 6 years ago
- Ethernet MAC 10/100 Mbps☆92Oct 2, 2019Updated 7 years ago
- Vim plugin for Bluespec SystemVerilog (BSV)☆12Nov 8, 2020Updated 5 years ago
- ☆17Sep 20, 2023Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.☆31Dec 1, 2016Updated 9 years ago
- A tiny example of PCM to PDM pipeline on FPGA☆23Feb 16, 2022Updated 4 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆90Oct 6, 2022Updated 4 years ago
- ☆11Dec 9, 2023Updated 2 years ago
- This is the checksum algorithm from the N64 bootrom (PIFROM) reverse engineered in C.☆11Jun 12, 2019Updated 7 years ago
- soc integration script and integration smoke script☆24Sep 12, 2022Updated 4 years ago
- Rust on LiteX SoC (icesugar + vexriscv).☆11Apr 20, 2026Updated 6 months ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆131Aug 29, 2022Updated 4 years ago
- A MkDocs plugin that uses heti to improve typesetting☆13Sep 30, 2023Updated 3 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- ☆40Oct 26, 2026Updated last week
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆32Jun 8, 2017Updated 9 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 8 years ago
- Cyclone V FPGA board for UnAmiga project☆11Sep 30, 2023Updated 3 years ago
- IP Cores that can be used within Vivado☆27May 18, 2021Updated 5 years ago
- ad7768-4 driver with stm32f446ZE,☆18Jul 19, 2020Updated 6 years ago
- The Brutzelkarte FPGA description code in VHDL☆15Jan 3, 2022Updated 4 years ago