Lampro-Mellon / QuasarLinks
Quasar 2.0: Chisel equivalent of SweRV-EL2
☆31Updated 4 years ago
Alternatives and similar repositories for Quasar
Users that are interested in Quasar are comparing it to the libraries listed below
Sorting:
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- Intel Compiler for SystemC☆26Updated 2 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- ☆89Updated last week
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 weeks ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- A Rocket-based RISC-V superscalar in-order core☆36Updated 2 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 6 months ago
- SCARV: a side-channel hardened RISC-V platform☆28Updated 2 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Updated last year
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- ☆33Updated 9 months ago
- Simple UVM environment for experimenting with Verilator.☆28Updated last month
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆23Updated last week
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.☆33Updated 5 years ago
- Chisel Cheatsheet☆34Updated 2 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated 2 weeks ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆47Updated last week
- A Heterogeneous GPU Platform for Chipyard SoC☆40Updated 2 weeks ago
- The RTL source for AnyCore RISC-V☆33Updated 3 years ago
- The multi-core cluster of a PULP system.☆110Updated last month
- Synthesisable SIMT-style RISC-V GPGPU☆48Updated 5 months ago
- A prototype GUI for chisel-development☆51Updated 5 years ago
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago