Lampro-Mellon / QuasarLinks
Quasar 2.0: Chisel equivalent of SweRV-EL2
☆31Updated 4 years ago
Alternatives and similar repositories for Quasar
Users that are interested in Quasar are comparing it to the libraries listed below
Sorting:
- Intel Compiler for SystemC☆26Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆68Updated last year
- A fault-injection framework using Chisel and FIRRTL☆36Updated 2 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- A Rocket-based RISC-V superscalar in-order core☆36Updated 2 months ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Updated last year
- ☆88Updated last week
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- Chisel Cheatsheet☆34Updated 2 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated 3 years ago
- Useful utilities for BAR projects☆32Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated last month
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated last week
- DUTH RISC-V Superscalar Microprocessor☆32Updated last year
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- A Heterogeneous GPU Platform for Chipyard SoC☆40Updated this week
- The RTL source for AnyCore RISC-V☆33Updated 3 years ago
- pulp_soc is the core building component of PULP based SoCs☆81Updated 8 months ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated 11 months ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆47Updated last month
- The multi-core cluster of a PULP system.☆109Updated last month
- ☆20Updated last month
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago