Quasar 2.0: Chisel equivalent of SweRV-EL2
☆34Apr 13, 2021Updated 5 years ago
Alternatives and similar repositories for Quasar
Users that are interested in Quasar are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆13Feb 13, 2021Updated 5 years ago
- ZC RISCV CORE☆12Dec 19, 2019Updated 6 years ago
- chipyard in mill :P☆77Nov 20, 2023Updated 2 years ago
- Useful utilities for BAR projects☆31Jan 3, 2024Updated 2 years ago
- ☆12May 20, 2021Updated 5 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- A standalone parser for BSV (Bluespec SystemVerilog) written in Go☆14Dec 20, 2016Updated 9 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- ☆29Jan 18, 2021Updated 5 years ago
- OmniXtend cache coherence protocol☆84Jun 10, 2025Updated last year
- ☆14Oct 30, 2024Updated last year
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆38Oct 23, 2025Updated 9 months ago
- (System)Verilog to Chisel translator☆121May 20, 2022Updated 4 years ago
- Consistency checker for memory subsystem traces☆23Oct 10, 2016Updated 9 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Feb 17, 2022Updated 4 years ago
- Import and export IP-XACT XML register models☆38Nov 5, 2025Updated 8 months ago
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated last year
- ☆10Nov 12, 2019Updated 6 years ago
- ☆61Aug 30, 2021Updated 4 years ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 2 years ago
- Andes Vector Extension support added to riscv-dv☆18May 29, 2020Updated 6 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆25Feb 1, 2020Updated 6 years ago
- Tang-Hex-BSP: BSP for ZYNQ 7020 based FPGA Board Tang-Hex☆13Apr 28, 2019Updated 7 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆40Feb 6, 2024Updated 2 years ago
- Binomial model☆12Aug 28, 2019Updated 6 years ago
- Branch Predictor Optimization for BlackParrot☆15Mar 24, 2024Updated 2 years ago
- All the tools you need to reproduce the CellIFT paper experiments☆24Feb 11, 2025Updated last year
- ☆43Updated this week
- Tile based architecture designed for computing efficiency, scalability and generality☆301Updated this week
- StateMover is a checkpoint-based debugging framework for FPGAs.☆22Jul 14, 2022Updated 4 years ago
- OpenScope Utility☆20Mar 17, 2020Updated 6 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆156Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆17Jan 1, 2021Updated 5 years ago
- Collaborative Execution Strategies for Heterogeneous CPU-FPGA Architectures☆11Apr 23, 2019Updated 7 years ago
- A simple, easily extendable, RISCV assembler for the RV32I subset in Python.☆31Aug 18, 2023Updated 2 years ago
- Network on Chip Implementation written in SytemVerilog☆209Aug 27, 2022Updated 3 years ago
- Modeling and Programming with Gecode☆50Jul 15, 2026Updated 2 weeks ago
- ☆17Jul 21, 2026Updated last week
- ☆15Dec 9, 2025Updated 7 months ago