Lampro-Mellon / QuasarLinks
Quasar 2.0: Chisel equivalent of SweRV-EL2
☆31Updated 4 years ago
Alternatives and similar repositories for Quasar
Users that are interested in Quasar are comparing it to the libraries listed below
Sorting:
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Updated last year
- For contributions of Chisel IP to the chisel community.☆66Updated 11 months ago
- Intel Compiler for SystemC☆25Updated 2 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated last month
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 3 months ago
- Useful utilities for BAR projects☆32Updated last year
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- Chisel Cheatsheet☆34Updated 2 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- ☆80Updated last week
- Synthesisable SIMT-style RISC-V GPGPU☆42Updated 3 months ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- A Rocket-based RISC-V superscalar in-order core☆35Updated 3 weeks ago
- The multi-core cluster of a PULP system.☆108Updated 3 weeks ago
- Workshop on Computer Architecture Research with RISC-V (CARRV)☆41Updated 11 months ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆59Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆67Updated last month
- Advanced Debug Interface☆14Updated 9 months ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆20Updated 5 months ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated last month
- Chisel Things for OFDM☆32Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆104Updated last month
- ☆50Updated last month
- A DMA Controller for RISCV CPUs☆13Updated 10 years ago